IP Library › Granted Patent US 11,778,822
Granted Patent B2
US 11,778,822 · App. 17/073,835 · Granted Oct 3, 2023

Semiconductor device and manufacturing method of the semiconductor device

Inventor: Jae Hyoung Lee (Icheon-si, KR)
Assignee: SK hynix Inc.
H10B43/27H10B41/27H10B63/34H10B63/845H10N70/066H10N70/231
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Quick Facts
Patent No.
US 11,778,822
App. No.
17/073,835
Granted
Oct 3, 2023
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming a first stack, forming a sacrificial structure and a first contact passing through the first stack, forming a second stack on the first stack, forming a first hole through the second stack to expose the sacrificial structure, forming a second hole through the first stack by removing the sacrificial structure, forming a channel structure in the first and second holes, and forming a second contact passing through the second stack and coupled to the first contact.

Claims (48)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a first stack in a cell region and a connection region;

forming a sacrificial structure in the cell region and a first contact in the connection region extending in a vertical direction in the first stack, simultaneously;

forming a second stack over the first stack;

forming a first hole through the second stack to expose the sacrificial structure;

forming a second hole through the first stack by removing the sacrificial structure;

forming a channel structure in the first and second holes; and

forming, after forming the channel structure, a second contact extending in the vertical direction in the second stack and coupled to the first contact.

2. The method according to claim 1 , further comprising:

forming a source structure and a first insulating layer disposed on a same level; and

forming a third contact extending in the vertical direction in the source structure and a fourth contact extending in the vertical direction in the first insulating layer,

wherein the fourth contact is coupled to the first contact.

3. The method according to claim 2 , wherein the source structure is coupled to the channel structure.

4. The method according to claim 2 , wherein a height of the third contact is the same as a height of the fourth contact.

5. The method according to claim 1 , wherein a height of the sacrificial structure is greater than a height of the first contact.

6. The method according to claim 1 , wherein a level of a boundary between the first and second contacts is the same as a level of a boundary between the first and second stacks.

7. The method according to claim 1 , further comprising:

replacing a first portion of a sacrificial pattern of the first stack with a conductive pattern, and retaining a second portion of the sacrificial pattern,

wherein the first portion encloses the channel structure, and

wherein the second portion encloses the first contact.

8. The method according to claim 1 , wherein a level of an upper surface of the sacrificial structure is the same as a level of an upper surface of the first contact.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a substrate;

forming an insulating structure over the substrate;

forming a source structure and a first insulating layer over the insulating structure;

forming a first contact extending in the vertical direction in the source structure and a second contact extending in the vertical direction in the first insulating layer;

forming, after forming the first contact and the second contact, a first stack over the first contact, the second contact, the source structure, and the first insulating layer;

forming a third contact extending in the vertical direction in the first stack and coupled to the second contact;

forming a second stack over the first stack; and

forming a fourth contact extending in the vertical direction in the second stack and coupled to the third contact.

10. The method according to claim 9 , further comprising:

forming a channel structure through the first and second stacks.

11. The method according to claim 10 , wherein forming the channel structure comprises:

forming a sacrificial structure through the first stack;

forming a first hole through the second stack to expose the sacrificial structure; and

removing the sacrificial structure.

12. The method according to claim 10 , wherein:

a sum of heights of the second, third, and fourth contacts is greater than a height of the channel structure, and

a sum of heights of the third and fourth contacts is smaller than the height of the channel structure.

13. The method according to claim 9 , wherein a width of an upper surface of the third contact is greater than a width of a lower surface of the fourth contact.

14. The method according to claim 13 , wherein the upper surface of the third contact is in contact with a lower surface of the second stack.

15. The method according to claim 13 , wherein a level of the upper surface of the third contact and a level of the lower surface of the fourth contact are the same as a level of a boundary between the first and second stacks.

16. The method according to claim 9 , further comprising:

forming a memory layer extending in the vertical direction in the first and second stacks,

wherein the memory layer comprises:

a first memory part extending in the vertical direction in the second stack, a second memory part extending in the vertical direction in the first stack, and a third memory part coupling the first memory part and the second memory part, and

wherein a level of an upper surface of the third memory part is the same as a level of a boundary between the third and fourth contacts.

17. The method according to claim 9 , wherein a height of the first contact is the same as a height of the second contact.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2020
From: LEE, JAE HYOUNG
To: SK HYNIX INC.
Reel/Frame 054096/0252 →
Priority Claims (1)
KR 10-2020-0058496 · May 15, 2020 · national
Continuity (1)
Related Publication 20210358943A1 · Nov 18, 2021