IP Library › Granted Patent US 11,782,708
Granted Patent B2
US 11,782,708 · App. 17/729,025 · Granted Oct 10, 2023

Arithmetic processing device and arithmetic processing method

Inventor: Akihiko Kasagi (Kawasaki, JP)
Assignee: FUJITSU LIMITED
G06F9/3001G06F9/3826G06F9/4411
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Quick Facts
Patent No.
US 11,782,708
App. No.
17/729,025
Granted
Oct 10, 2023
Kind
B2
Abstract

An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the measured processing time.

Claims (16)

1. An arithmetic processing device comprising:

a memory; and

a processor coupled to the memory and configured to:

execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings;

measure a processing time of each of the plurality of pipeline stages;

set a priority of the plurality of pipeline stages in a descending order of the measured processing time; and

change the priority for each of the plurality of pipeline stages by hooking an application programmable interface of a driver that controls an operation of the processor.

2. The arithmetic processing device according to claim 1 , wherein a measurement of the processing time and a setting of the priority are performed before an execution of the plurality of data processes.

3. The arithmetic processing device according to claim 1 , wherein the processor hooks a function which generates a queue with no priority by the application programmable interface of the driver and a function which generates a queue with a priority by the application programmable interface of the driver.

4. An arithmetic processing method comprising:

executing, by a processor, a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings;

measuring a processing time of each of the plurality of pipeline stages;

setting a priority of the plurality of pipeline stages in a descending order of the measured processing time; and

changing the priority for each of the plurality of pipeline stages by hooking an application programmable interface of a driver that controls an operation of the processor.

5. The arithmetic processing method according to claim 4 , wherein a measurement of the processing time and a setting of the priority are performed before an execution of the plurality of data processes.

6. The arithmetic processing method according to claim 4 , wherein a function which generates a queue with no priority by the application programmable interface of the driver and a function which generates a queue with a priority by the application programmable interface of the driver are hooked.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2022
From: KASAGI, AKIHIKO
To: FUJITSU LIMITED
Reel/Frame 059791/0857 →
Priority Claims (1)
JP 2021-112534 · Jul 7, 2021 · national
Continuity (1)
Related Publication 20230010536A1 · Jan 12, 2023