Gate driver for separately charging a node voltage of buffers and display device including the same
Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q′ node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.
1. A gate driver comprising:
a plurality of stage circuits,
wherein each of the plurality of stage circuits comprises:
a shift register configured to control charging and discharging of a Q node and a QB node; and
a plurality of output buffers sequentially connected to the shift register,
wherein each of the output buffers comprises:
a first transistor configured to transmit a voltage of the Q node to a Q′ node, the first transistor including a gate electrode, a first electrode, and a second electrode that is connected to the Q node;
a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, the pull-up transistor including a gate electrode that is connected to the first electrode of the first transistor;
a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node, and
wherein each of the output buffers further comprises a second transistor turned on according to the voltage of the Q node and configured to charge the Q′ node with a high-potential voltage, the second transistor including a gate electrode that is connected to the Q node, a first electrode that is connected to a power line that supplies the high-potential voltage, and a second electrode that is connected to the first electrode of the first transistor and the gate electrode of the pull-up transistor.
2. The gate driver of claim 1 , wherein the gate electrode of the first transistor is connected to the power line that supplies the high-potential voltage that is a direct current power source.
3. The gate driver of claim 1 , wherein each of the output buffers further comprises a third transistor turned on according to the voltage of the QB node and configured to discharge the Q′ node.
4. The gate driver of claim 3 , wherein the first transistor is connected in a form of a diode between the Q node and the Q′ node.
5. The gate driver of claim 3 , wherein the gate electrode of the first transistor is configured to receive a carry signal output from a previous stage circuit.
6. The gate driver of claim 3 , wherein the gate electrode of the first transistor is configured to receive the high-potential voltage that is a direct current power source or receive a carry signal output from a previous stage circuit.
7. The gate driver of claim 3 , wherein the first transistor is connected in a form of a diode between the Q node and the Q′ node.
8. The gate driver of claim 3 , wherein the first transistor and the second transistor are configured to separately control charging and discharging of each Q node of the plurality of output buffers.
9. A display device comprising:
a display panel configured to display an image;
a data driver configured to apply a data signal to the display panel; and
a gate driver comprising a plurality of stage circuits and configured to apply a gate signal to the display panel,
wherein each of the plurality of the stage circuits comprises:
a shift register configured to control charging and discharging of a Q node and a QB node; and
a plurality of output buffers sequentially connected to the shift register,
wherein each of the output buffers comprises:
a first transistor configured to transmit a voltage of the Q node to a Q′ node, the first transistor including a gate electrode, a first electrode, and a second electrode that is connected to the Q node;
a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, the pull-up transistor including a gate electrode that is connected to the first electrode of the first transistor; and
a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node, and
wherein each of the output buffers further comprises a second transistor turned on according to the voltage of the Q node and configured to charge the Q′ node with a high-potential voltage, the second transistor including a gate electrode that is connected to the Q node, a first electrode that is connected to a power line that supplies the high-potential voltage, and a second electrode that is connected to the first electrode of the first transistor and the gate electrode of the pull-up transistor.
10. The display device of claim 9 , wherein the gate electrode of the first transistor is connected to the power line that supplies the high-potential voltage that is a direct current power source.
11. The display device of claim 9 , wherein each of the output buffers further comprises a third transistor turned on according to the voltage of the QB node and configured to discharge the Q′ node.
12. The display device of claim 11 , wherein the first transistor is connected in a form of a diode between the Q node and the Q′ node.
13. The display device of claim 11 , wherein the power line that supplies gate electrode of the first transistor is configured to receive a carry signal output from a previous stage circuit.
14. The display device of claim 11 , wherein the gate electrode of the first transistor is configured to receive the high-potential voltage that is a direct current power source or receive a carry signal output from a previous stage circuit.
15. The display device of claim 11 , wherein the first transistor is connected in a form of a diode between the Q node and the Q′ node.