Edge memory array mats with sense amplifiers
An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.
1. An apparatus comprising:
a memory array mat comprising:
a first pair of access line segments each having an end configured to couple to a sense amplifier formed in a common region of the memory array mat; and
a combined access line segment comprising a second pair of access line segments each having an end configured to couple together across the common region, wherein the combined access line segment is coupled to a second sense amplifier formed adjacent an outside edge of the memory array mat between the memory array mat and an inner memory array mat.
2. The apparatus of claim 1 , further comprising an access line jumper configured to electrically couple the second pair of access line segments together.
3. The apparatus of claim 2 , wherein the access line jumper has a metal layer that is formed at a different plane than the second pair of access line segments.
4. The apparatus of claim 1 , wherein each of the first pair of access line segments and each of the second pair of access line segments are coupled to a same number of memory cell rows.
5. The apparatus of claim 1 , wherein the combined access line segment is coupled to a first number of memory cell rows and each of the first pair of access line segments are coupled to a second number of memory cell rows.
6. The apparatus of claim 5 , wherein the first number of memory cell rows is greater than the second number of memory cell rows.
7. The apparatus of claim 1 , further comprising a bank of sense amplifiers that includes the first sense amplifier bank formed in the common region.
8. The apparatus of claim 7 , further comprising a second bank of sense amplifiers that includes the second sense amplifier bank formed adjacent the outside edge of the memory array mat.
9. The apparatus of claim 1 , wherein the first sense amplifier is schematically equivalent to the second sense amplifier.
10. The apparatus of claim 1 , wherein the first sense amplifier is schematically different than the second sense amplifier.
11. The apparatus of claim 1 , wherein the second sense amplifier includes threshold voltage compensation circuitry.
12. A method comprising:
forming first and second access lines each including a respective gap at a common region within a memory array mat;
coupling respective ends of the first access line adjacent the common region to a first sense amplifier formed in the common region;
coupling respective ends of the second access line adjacent the common region together to form a combined access line; and
electrically coupling one end of the combined access line to a second sense amplifier formed adjacent an outside edge of the memory array mat between the memory array mat and an inner memory array mat.
13. The method of claim 12 , further comprising forming an access line jumper to electrically couple a second pair of access line segments together.
14. The method of claim 13 , further comprising forming the access line jumper with a metal layer that is included at a different plane than the second line.
15. The method of claim 12 , further comprising coupling the first and second access line segment to a same number of memory cell rows.
16. The method of claim 12 , wherein the first sense amplifier is configured to be coupled to any of a first number of memory cell rows and the second sense amplifier is configured to be coupled to any of a second number of memory cell rows that is greater than the first number.
17. The method of claim 12 , further comprising forming a bank of sense amplifiers that includes the first sense amplifier bank in the common region.
18. The method of claim 17 , further comprising forming a second bank of sense amplifiers that includes the second sense amplifier bank adjacent the outside edge of the memory array mat.
19. The method of claim 12 , further comprising forming the first sense amplifier and the second sense amplifier using schematically equivalent circuitry.
20. The method of claim 12 , further comprising forming the first sense amplifier and the second sense amplifier using schematically different circuitry.