Semiconductor device and method of manufacture
A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.
1. A method comprising:
forming a plurality of first redistribution layers over a carrier;
attaching a first internal support to the plurality of first redistribution layers, wherein the first internal support is an electrically inert material;
forming a plurality of second redistribution layers over the plurality of first redistribution layers and over the first internal support;
attaching a first interconnect substrate and a second interconnect substrate to the plurality of second redistribution layers, wherein the first interconnect substrate is laterally separated from the second interconnect substrate by a gap, wherein the gap is laterally aligned with the first internal support; and
attaching a plurality of integrated circuit dies to the plurality of first redistribution layers.
2. The method of claim 1 , wherein the plurality of first redistribution layers is formed using a different technique than the plurality of second redistribution layers.
3. The method of claim 1 , further comprising depositing an underfill material on the first interconnect structure and the second interconnect structure.
4. The method of claim 1 , wherein the first internal support is attached to the plurality of first redistribution layers using a die attach film.
5. The method of claim 1 , wherein the first internal support comprises ceramic.
6. The method of claim 1 further comprising attaching a second internal support to the plurality of first redistribution layers.
7. The method of claim 1 , wherein the plurality of second redistribution layers comprise a different dielectric material than the plurality of first redistribution layers.
8. The method of claim 1 , wherein the first internal support has a length in the range of 2 mm to 60 mm.
9. A method comprising:
attaching a plurality of first dummy dies to a first redistribution structure, wherein the first dummy dies comprise an insulating material;
forming a second redistribution structure on the first redistribution structure and the plurality of first dummy dies, wherein the second redistribution structure is electrically coupled to the first redistribution structure; and
attaching a plurality of interconnect structures to the second redistribution structure, wherein the plurality of interconnect structures are electrically coupled to the second redistribution structure, wherein at least one first dummy die of the plurality of first dummy dies laterally overlaps at least two respective interconnect structures of the plurality of interconnect structures.
10. The method of claim 9 further comprising forming a first dielectric layer over the plurality of first dummy dies.
11. The method of claim 10 further comprising planarizing the first dielectric layer to expose top surfaces of the plurality of first dummy dies.
12. The method of claim 9 further comprising attaching a plurality of second dummy dies to a third redistribution structure, wherein the first redistribution structure is formed on the third redistribution structure.
13. The method of claim 12 , wherein at least one first dummy die laterally overlaps at least one second dummy die.
14. The method of claim 9 further comprising connecting a semiconductor device to the first redistribution structure opposite the second redistribution structure.
15. The method of claim 14 , wherein the semiconductor device comprises a plurality of semiconductor dies, wherein at least one first dummy die of the plurality of first dummy dies laterally overlaps at least two respective semiconductor dies of the plurality of semiconductor dies.
16. The method of claim 9 , wherein the dummy die comprises silicon carbide.
17. A method comprising:
forming a first redistribution structure, comprising:
forming a first metallization pattern on a first dielectric layer;
placing an internal support structure on the metallization pattern;
forming a second dielectric layer over the first metallization pattern and the internal support structure; and
forming a second metallization pattern on the second dielectric layer, wherein the second metallization pattern is electrically coupled to the first metallization pattern;
connecting a first core substrate to the first redistribution structure, wherein the first core substrate extends over the internal support structure; and
connecting a second core substrate to the first redistribution structure, wherein the second core substrate extends over the internal support structure.
18. The method of claim 17 , wherein the internal support structure comprises a metal.
19. The method of claim 17 , wherein the second metallization pattern physically contacts the internal support structure.
20. The method of claim 17 further comprising connecting a third core substrate to the first redistribution structure, wherein the third core substrate extends over the internal support structure.