Granted Patent B2

US 11,784,668 · App. 17/666,066 · Granted Oct 10, 2023

Inventors: Damian Alfonso Morero (Santa Clara, CA); Mario Alejandro Castrillion (Santa Clara, CA); Matias German Schnidrig (Santa Clara, CA); Mario R. Hueda (Santa Clara, CA)

Assignee: Marvell Asia Pte, Ltd

H03M13/616H03M13/112H03M13/116H03M13/1137H03M13/6577

Abstract

Claims (35)

1. A decoder for a receiver in a communication system, the decoder comprising:

an interface configured to receive encoded input data via a communication channel, the encoded input data including forward error correction (FEC) codewords;

a processor configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix, the parity check matrix being defined by both (i) regular column partition (RCP) constraints and (ii) quasi-cyclic (QC) constraints, the processor being further configured to perform a plurality of decoding iterations to decode the FEC codewords, each of the plurality of decoding iterations comprising using a respective one of a plurality of sub-matrices of the parity check matrix,

wherein

the processor comprises

a plurality of check node processing circuits configured to compute, during each of the plurality of decoding iterations, first messages based on row values of the sub-matrix used for the respective one of the plurality of decoding iterations, and

a plurality of variable node processing circuits configured to compute, during each of the plurality of decoding iterations, second messages based on the first messages and column values of the sub-matrix used for the respective one of the plurality of decoding iterations, and

wherein at least one of i) a total number of first messages computed by the plurality of check node processing circuits during each of the plurality of decoding iterations is equal to a number of 1s in each row of the sub-matrix used for the respective one of the plurality of decoding iterations, and ii) a total number of second messages computed by the plurality of variable node processing circuits during each of the plurality of decoding iterations is equal to a number of 1s in each column of the sub-matrix used for the respective one of the plurality of decoding iterations; and

an output circuit configured to output a decoded codeword based on the FEC codewords decoded by the processor.

2. The decoder of claim 1 , each row of the parity check matrix corresponding to a parity check of a respective FEC codeword and each column of the parity check matrix corresponding to a portion of the respective FEC codeword.

3. The decoder of claim 2 , the processor being configured to apply an iterative decoding algorithm in which a different column of the parity check matrix is processed in each iteration of the iterative decoding algorithm.

4. The decoder of claim 3 , the processor being configured to apply the iterative decoding algorithm to (i) process a first portion of a first FEC codeword and (ii) process a first portion of a second FEC codeword prior to processing a second portion of the first FEC codeword.

5. The decoder of claim 3 , the processor being configured to apply the iterative decoding algorithm to simultaneously process respective portions of a first FEC codeword and a second FEC codeword.

6. The decoder of claim 1 , wherein the FEC codewords are non-concatenated FEC codewords.

7. The decoder of claim 1 , wherein a circular shift of a row of the parity check matrix by an integer amount results in a valid FEC codeword.

8. The decoder of claim 1 , each row of the parity check matrix corresponding to a cyclic shift of an adjacent row of the parity check matrix.

9. The decoder of claim 1 , wherein the parity check matrix is (i) row-regular such that each row has a same number of 1s and (ii) column-regular such that each column has a same number of 1s.

10. The decoder of claim 1 , the parity check matrix comprising an array of circulant sub-matrices, each of the circulant sub-matrices comprising a square matrix in which a first row is a cyclic shift of a last row, and each other row is a cyclic shift of a directly-above row.

11. The decoder of claim 1 , the processor comprising a plurality of check node processing units each configured to receive a respective one of the FEC codewords and perform, in parallel with others of the plurality of check node processing units, a check node computation on the respective one of the FEC codewords using a different row of the parity check matrix.

12. The decoder of claim 1 , wherein each of the FEC codewords has a length comprising a first integer multiple of a power of 2, and each decoded codeword has an effective code dimension of a second integer multiple of the power of 2.

13. A receiver comprising the decoder of claim 1 .

14. A communication system comprising the receiver of claim 13 and further comprising a transmitter, the transmitter comprising an encoder configured to encode the FEC codewords.

15. The decoder of claim 1 , wherein a total number of the plurality of variable node processing circuits of the decoder is less than a total number of columns in the parity check matrix.

16. The decoder of claim 1 , wherein the total number of the plurality of variable node processing circuits of the decoder is equal to a number of columns in each of the plurality of sub-matrices.

17. The decoder of claim 1 , wherein the plurality of variable node processing circuits are configured to iteratively sum first extrinsic information from the plurality of check node processing circuits, the first extrinsic information being indicative of a probability of whether a received bit of the input data is a 0 or a 1.

18. The decoder of claim 17 , wherein the plurality of variable node processing circuits are configured, when summing the first extrinsic information, to receive log-likelihood ratios corresponding to 1 s in a column of a respective one of the plurality of sub-matrices.

19. The decoder of claim 18 , wherein the plurality of check node processing circuits are configured to iteratively sum second extrinsic information received from the plurality of variable node processing circuits.

20. The decoder of claim 1 , further comprising a memory configured to store the FEC codewords, wherein:

during a first one of the plurality of decoding iterations, each of the plurality of variable node processing circuits is configured to receive from the memory i) a bit of one of the FEC codewords, and ii) log-likelihood ratios corresponding to bits from a row of a first one of the plurality of sub-matrices; and

the plurality of check node processing circuits are configured, during the decoding iterations other than the first one of the plurality of decoding iterations, to receive the second messages from the plurality of variable node processing circuits.

21. The decoder of claim 1 , wherein the plurality of check node processing circuits are configured i) during a first one of the plurality of decoding iterations, to receive portions of the FEC codewords provided from the interface to the plurality of check node processing circuits, and ii) during the decoding iterations other than the first one of the plurality of decoding iterations, to receive the second messages from the plurality of variable node processing circuits.

22. The decoder of claim 1 , wherein the plurality of check node processing circuits is configured to operate on a first one of the FEC codewords while operating on a second one of the FEC codewords.

23. The decoder of claim 1 , wherein:

the FEC codewords comprise a first FEC codeword and a second FEC codeword; and

the processor is configured to process a first iteration of the first FEC codeword followed by processing a first iteration of the second FEC codeword, and, subsequent to processing the first iteration of the second FEC codeword, to process a second iteration of the first FEC codeword.

Continuity (8)