Detection and mitigation of unstable cells in unclonable cell array
A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.
1. A circuit comprising:
a plurality of bit generating cells;
at least one characterization circuit coupled to influence outputs of the bit generating cells, the characterization circuit comprising:
a first inverter;
a second inverter;
at least one pass-gate circuit coupled between the first inverter and the second inverter;
logic to select and apply, based on varying an input and a bias of the first inverter, the outputs of a subset less than all of the bit generating cells.
2. The circuit of claim 1 , wherein the circuit comprises an unclonable cell array.
3. The circuit of claim 2 , the unclonable cell array configured to generate an encryption key.
4. The circuit of claim 1 , wherein at least one of the bit generating cells comprises a plurality of stages, each stage comprising more inverters arranged in parallel than an immediately preceding stage.
5. The circuit of claim 4 , further comprising at least one stage of inverters arranged in series.
6. The circuit of claim 1 , wherein an output of the second inverter is coupled to an input of the second inverter.
7. The circuit of claim 1 , wherein the at least one pass-gate circuit comprises a plurality of pass-gate circuits arranged in parallel.
8. The circuit of claim 7 , the plurality of pass-gate circuits configured to receive a control code.
9. An encryption key generating circuit comprising:
an unclonable cell array;
at least one characterization circuit to vary inputs to bit generating cells in the unclonable cell array;
the characterization circuit comprising a series arrangement of a first inverter, a second inverter, and a resistance coupled between the first inverter and the second inverter; and
logic to configure a subset of the bit generating cells to generate the encryption key based on results of operating the characterization circuit.
10. The encryption key generating circuit of claim 9 , wherein the resistance comprises at least one pass-gate circuit.
11. The encryption key generating circuit of claim 10 , wherein the resistance comprises a plurality of pass-gate circuits arranged in parallel.
12. The encryption key generating circuit of claim 11 , wherein the plurality of pass-gate circuits are configured to receive a digital control code to control the resistance value.
13. The encryption key generating circuit of claim 9 , wherein at least some of the bit generating cells comprise a plurality of stages, each of the stages comprising inverters arranged in parallel.
14. The encryption key generating circuit of claim 13 , wherein the fanout increases between each of the stages.
15. A method comprising:
operating at least one characterization circuit to introduce changes to outputs of a plurality of bit generating cells;
varying a resistance of the characterization circuit to introduce the changes; and
selecting a subset less than all of the bit generating cells as a key value based the changes to the outputs.
16. The method of claim 15 , further comprising varying an input and a bias signal of the characterization circuit to introduce the changes.
17. The method of claim 15 , further comprising applying the key value as a master key to authenticate a software application.
18. The method of claim 15 , further comprising applying the key value to perform encryption.
19. The method of claim 15 , further comprising arranging the bit generating cells into an unclonable cell array.