Centralized aggregated elephant flow detection and management

1. A semiconductor chip for implementing aggregated flow detection and management, the semiconductor chip comprising:

a plurality of pipes, each pipe being coupled to a portion of ports on the semiconductor chip that are configured to receive data packets; and

a logic coupled to the plurality of pipes and configured to detect and manage an elephant flow,

wherein the logic includes a flow table and a byte counter, wherein the logic is configured to:

receive, for each data packet, flow information, an ingress port, and an egress port in the data packet;

receive, for the data packet, live updates on flow information from the ports;

detect and manage the elephant flow based on at least the flow information;

notify, in response to evicting the flow, a corresponding ingress port to perform at least one of taking a programmed action or sending an evicted flow into software.

2. The semiconductor chip of claim 1 , wherein the logic is configured to receive, for each data packet, a count of bytes in the data packet.

3. The semiconductor chip of claim 2 , wherein the flow information comprises a count of different values corresponding to a transmission control protocol, a source port address, a destination port address and an associated transmission protocol.

4. The semiconductor chip of claim 2 , wherein the count of the bytes in the data packet is derived from an end-of-packet (EOP) and is used to enable flow-detection support associated with a transmission protocol, irrespective of availability of data packet lengths in header bytes of the transmission protocol.

5. The semiconductor chip of claim 1 , wherein the logic further comprises a flow-aging logic implemented on the semiconductor chip, wherein an entire logic is implemented on the semiconductor chip once, irrespective of a count of pipes on the semiconductor chip, and is aggregated across all pipes on the semiconductor chip.

6. The semiconductor chip of claim 5 , wherein the logic is configured to track flows across the semiconductor chip to detect the elephant flow.

7. The semiconductor chip of claim 6 , wherein the logic is configured to track the flows across the semiconductor chip by comparing a per-flow accumulated byte count against configurable byte-count and time-period thresholds to detect the elephant flow.

8. The semiconductor chip of claim 7 , wherein the logic is further configured to report the detected elephant flow and support aging of the detected elephant flow within a configurable interval, wherein the flow-aging logic is configured to evict a flow if there is no update on the flow, the per-flow accumulated byte count is lower than a corresponding programmed threshold for a programmed time duration, or a traffic congestion on an egress port eases.

9. The semiconductor chip of claim 7 , wherein the logic is agnostic to an elephant flow changing ingress ports of a given router.

10. The semiconductor chip of claim 1 , wherein each pipe of the plurality of pipes is configured to provide a flow hash calculated on the flow information.

11. The semiconductor chip of claim 10 , wherein the logic is configured to track the flow hash if a corresponding egress port is congested and/or loaded to a certain threshold for a predefined time interval.

12. The semiconductor chip of claim 10 , wherein the flow table comprises a load-aware equal-cost multipath (ECMP) group table including group base and size information.

13. A method of detection and management of an aggregated flow, the method comprising:

configuring a pipe of a plurality of pipes disposed on a semiconductor chip to receive a data packet from a port of a plurality of ports of the semiconductor chip;

coupling a logic to the plurality of pipes; and

configuring the logic to:

receive, for the data packet, live updates on flow information from the plurality of ports;

detect and manage an elephant flow based on at least the flow information;

collect additional information on a ECMP group size and corresponding next hops when information on elephant flows and a corresponding flow hash exists;

use information on the elephant flows and the corresponding flow hash to automatically derive a desired destination to segregate or distribute the elephant flows; and

notify, in response to evicting the flow, a corresponding ingress port to perform at least one of taking a programmed action or sending an evicted flow into software.

14. The method of claim 13 , further comprising configuring the logic to receive live updates regarding an ingress port, an egress port and a count of bytes in the data packet.

15. The method of claim 14 , further comprising configuring the logic to:

derive the count of the bytes in the data packet from an EOP, and

enable detection support for a transmission protocol irrespective of availability of data packet lengths.

16. The method of claim 13 , further comprising configuring the logic to:

examine each data packet from a given pipe to determine whether an associated flow entry exists, and

create and update a corresponding counter when the associated flow entry does not exist.

17. A method of detection and management of an aggregated flow, the method comprising:

configuring a pipe of a plurality of pipes disposed on a semiconductor chip to receive a data packet from a port of a plurality of ports of the semiconductor chip;

coupling a logic to the plurality of pipes; and

configuring the logic to:

receive, for the data packet, live updates on flow information from the plurality of ports;

detect and manage an elephant flow based on at least the flow information;

examine each data packet from a given pipe to determine whether an associated flow entry exists;

create and update a corresponding counter when the associated flow entry does not exist;

update changes to ingress ports and/or egress ports and corresponding counters, when the associated flow entry exists,

compare an accumulated byte count, per flow, against configurable byte-count and time-period thresholds,

notify a corresponding ingress pipeline to take a programmed action or send the flow information to software,

aggregate byte counts for given flows from all pipes and different filters; and

evict a flow if there is no update on the flow or the aggregated byte count is lower than a corresponding programmed threshold for a programmed time duration or traffic congestion on an egress port eases.

18. The method of claim 17 , further comprising configuring the logic to:

collect additional information on a ECMP group size and corresponding next hops when information on elephant flows and a corresponding flow hash exists;

use information on the elephant flows and the corresponding flow hash to automatically derive a desired destination to segregate or distribute the elephant flows; and

notify, in response to evicting the flow, a corresponding ingress port to perform at least one of taking the programmed action or sending an evicted flow into software.

19. A system comprising:

memory; and

one or more processors coupled to the memory and configured to execute instructions to perform acts including:

receiving, by a pipe of a plurality of pipes disposed on a semiconductor chip, data packets from a plurality of ports of the semiconductor chip;

receiving, by an logic, live updates on flow information regarding the data packets from the plurality of ports; and

detecting and managing an elephant flow based at least on the flow information,

collecting additional information on a ECMP group size and corresponding next hops when information on elephant flows and a corresponding flow hash exists;

using information on the elephant flows and the corresponding flow hash to automatically derive a desired destination to segregate or distribute the elephant flows; and

notifying, in response to evicting the flow, a corresponding ingress port to perform at least one of taking a programmed action or sending an evicted flow into software;

wherein the logic is coupled to the plurality of pipes.

20. A system comprising:

memory; and

one or more processors coupled to the memory and configured to execute instructions to perform acts including:

receiving, by a pipe of a plurality of pipes disposed on a semiconductor chip, data packets from a plurality of ports of the semiconductor chip;

receiving, by logic, live updates on flow information regarding the data packets from the plurality of ports;

detecting and managing an elephant flow based at least on the flow information,

wherein the logic is coupled to the plurality of pipes; and

tracking a flow hash when data traffic congestion occurs at a corresponding egress port;

notifying a corresponding pipe to record an entire flow information corresponding to the flow hash when an elephant flow is detected;

configuring a separate pipe to automatically increment or decrement a priority level of data packets in a detected elephant flow;

causing the corresponding pipe to report the detected elephant flow to software using first-in-first-out (FIFO) direct memory access (DMA); and

leveraging the flow hash to segregate or distribute the detected elephant flow across a desired destination port or a selected set of destination ports using a load-aware ECMP structure.