Method of realizing a hardware device for executing operations defined by a high-level software code
This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm.
1. A computer-implemented method of realizing a hardware device for executing operations defined by a high-level software code, the method comprising the steps of:
translating said high-level software code into a corresponding low-level software code for executing the same operations defined by the high-level software code, wherein said low-level software code defines low-level operations;
for each hardware device of a set of hardware devices that can be manufactured or configured for executing said low-level software code, carrying out the following operations:
estimating, for each low-level operation and for each type of hardware resources of said hardware device, an usage amount of hardware resources of said type required for implementing said low-level operation with said hardware device, wherein said estimating step is carried out assuming that there are no data dependencies among said low-level operations,
for each low-level operation of said low-level operations, estimating a number of run-time occurrences of said low-level operation in said low-level software code,
calculating, for each type of said available hardware resources a corresponding number of required hardware resources of said type as the summation, over all said low-level operations, of the product between the number of run-time occurrence of said low-level operation and the corresponding usage amount of said type of available hardware resources,
calculating, for each type of said available hardware resources, a corresponding ratio between said number of required hardware resources and a defined amount of the available hardware resources in said hardware device of said type of available hardware resources,
calculating a scale factor for said hardware device as a maximum value of said ratios calculated in the previous step,
calculating a peak performance value of said hardware device as a summation, over all said low-level operations, of the product of said number of run-time occurrence of said low-level operations by a rate defining a number of low-level operations per second that may be carried out by the hardware device, divided by said scale factor;
choosing the hardware device to be manufactured or configured out of said set of hardware devices that may be manufactured or configured, depending upon said respective peak performance value calculated for each hardware device of said set;
manufacturing or configuring said hardware device, chosen in the previous step, to carry out said high-level software code.
2. The method of claim 1 , wherein, for each hardware device of said set, the method comprises the steps of:
estimating a total number of bytes of data to be transferred to and from a memory of said hardware device when the software code is executed,
calculating an operational intensity of the low-level software code as a summation, over all said low-level operations, of the ratios between the number of run-time occurrences (o op ) of said low-level operation and total number of bytes of data to be transferred to and from the memory,
estimating a maximum bandwidth for transferring data to and from the memory of said hardware device,
calculating a memory transfer performance value of said hardware device as the product of said operational intensity by said maximum bandwidth,
choosing the hardware device of said set to be manufactured or configured, also depending upon said respective memory transfer performance value calculated for each hardware device of said set.
3. The method of claim 2 , wherein said hardware device is configured on a FPGA or manufactured as an ASIC and said step of realizing said hardware device comprises the step of executing a Design Space Exploration algorithm on said low-level software code for identifying a suitable FPGA configuration or an ASIC based on said peak performance value and memory transfer performance value to be met.
4. The method of claim 2 , wherein said operational intensity are calculated over a sub set of low-level operations of said low-level operations of the low-level software code.
5. The method of claim 1 , wherein said low-level software code is generated by:
transforming, with a LLVM front-end compiler, said high-level software code into said low-level software code;
processing said low-level software code with a LLVM compiler for estimating said number of run-time occurrences and said usage amount.
6. The method of claim 1 , further comprising the step of estimating said usage amount of each type of hardware resources of said hardware device by a resource estimation algorithm for each low-level operation of said low-level operations.
7. The method of claim 1 , wherein said type of hardware resources are Block RAM, DSP, Flip-Flops, Look Up Tables and area.
8. The method of claim 1 , wherein said peak performance value is calculated over a subset of low-level operations of said low-level operations of the low-level software code.