Collateral correlated regression in version control repository
A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.
1. A computer-implemented method, comprising:
identifying a register-transfer-level (RTL) design;
converting the RTL design into a control data flow graph having a plurality of nodes and a plurality of arcs;
generating a mapping table with a machine learning database from a set of test cases based on the control data flow graph; and
selectively calling one or more test cases of the set of test cases to merge a branch to a main repository.
2. The method of claim 1 , wherein each node of the plurality of nodes of the control data flow graph is a logical expression.
3. The method of claim 1 , wherein each arc of the plurality of arcs is a signal to at least one node of the plurality of nodes.
4. The method of claim 1 , wherein the mapping table is generated by parsing the set of test cases in regressions through the control data flow graph.
5. The method of claim 4 , wherein the mapping table indicates each node and arc traversed by each test case of the set of test cases.
6. The method of claim 1 , further comprising:
determining a test case efficiency for at least one test case of the set of test cases.
7. The method of claim 6 , further comprising:
testing one or more logic cones based on the test case efficiency of the at least one test case.
8. A system, comprising:
one or more processors; and
a computer-readable storage medium, coupled to the one or more processors, storing program instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
converting a register transfer level (RTL) design into a control data flow graph having a plurality of nodes and a plurality of arcs;
generating a mapping table with a machine learning database from a set of test cases based on the control data flow graph; and
selectively calling one or more test cases of the set of test cases to merge a branch to a main repository.
9. The system of claim 8 , wherein each node of the plurality of nodes of the control data flow graph is a logical expression.
10. The system of claim 8 , wherein each arc of the plurality of arcs is a signal to at least one node of the plurality of nodes.
11. The system of claim 8 , wherein the mapping table is generated by parsing the set of test cases in regressions through the control data flow graph.
12. The system of claim 11 , wherein the mapping table indicates each node and arc traversed by each test case of the set of test cases.
13. The system of claim 8 , wherein the operations further comprise:
determining a test case efficiency for at least one test case of the set of test cases.
14. The system of claim 13 , wherein the operations further comprise:
testing one or more logic cones based on the test case efficiency of the at least one test case.
15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by one or more processors to cause the one or more processors to perform operations comprising:
converting a register transfer level (RTL) design into a control data flow graph having a plurality of nodes and a plurality of arcs;
generating a mapping table with a machine learning database from a set of test cases based on the control data flow graph; and
selectively calling one or more test cases of the set of test cases to merge a branch to a main repository.
16. The computer program product of claim 15 , wherein each node of the plurality of nodes of the control data flow graph is a logical expression.
17. The computer program product of claim 15 , wherein each arc of the plurality of arcs is a signal to at least one node of the plurality of nodes.
18. The computer program product of claim 15 , wherein the mapping table is generated by parsing the set of test cases in regressions through the control data flow graph.
19. The computer program product of claim 18 , wherein the mapping table indicates each node and arc traversed by each test case of the set of test cases.
20. The computer program product of claim 15 , wherein the operations further comprise:
determining a test case efficiency for at least one test case of the set of test cases; and
testing one or more logic cones based on the test case efficiency of the at least one test case.