Memory system

1. A memory system comprising:

a nonvolatile memory; and

a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device,

wherein the memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more, the first number being a number of the first requests to be performed in the memory controller, the first threshold value being an integer of 2 or more.

2. The memory system according to claim 1 , wherein:

the memory controller is further configured to interrupt the second process when a first period becomes a second threshold value or more while holding the interruption of the second process; and

the first period is a consecutive period during which the first number is 1 or more.

3. The memory system according to claim 1 , wherein:

the memory controller is further configured to interrupt the second process when a second period becomes a third threshold value or more while holding the interruption of the second process and the first number is 1 or more; and

the second period is a consecutive period during which the second process is being executed and does not include a period during which the second process is being interrupted.

4. The memory system according to claim 3 , wherein a starting point of the second period is when the second process is started.

5. The memory system according to claim 3 , wherein a starting point of the second period is when the second process is resumed from interruption.

6. The memory system according to claim 1 , wherein:

the memory controller is further configured to hold resuming of the interrupted second process until a third period becomes a fourth threshold value or more while the second process is being interrupted; and

the third period is a consecutive period during which the second process is being interrupted.

7. The memory system according to claim 1 ,

wherein the memory controller is configured to, while the second process is being interrupted:

cause the nonvolatile memory to execute the first process; and

hold resuming of the interrupted second process until a fourth period becomes a fifth threshold value or more, and

wherein the fourth period is a consecutive period during which the second process is being interrupted and the first process is not being executed.

8. The memory system according to claim 1 , wherein:

the memory controller is further configured to resume the interrupted second process when a fifth period becomes a sixth threshold value or more while the second process is being interrupted; and

the fifth period is a period during which the second process is being interrupted.

9. The memory system according to claim 8 , wherein the fifth period is a consecutive period.

10. The memory system according to claim 8 , wherein the fifth period is a cumulative period of one or more periods during which the second process is being interrupted.

11. The memory system according to claim 1 , wherein:

the memory controller is further configured to change the first threshold value on the basis of characteristics of a workload of the memory system or a second request from the host device; and

the characteristics of the workload include at least one of the first number, an idle time of the memory system, and an amount of data received from the host device to be written in the nonvolatile memory.

12. The memory system according to claim 2 , wherein:

the memory controller is further configured to change the second threshold value on the basis of characteristics of a workload of the memory system or a second request from the host device; and

the characteristics of the workload include at least one of the first number, an idle time of the memory system, and an amount of data received from the host device to be written in the nonvolatile memory.

13. The memory system according to claim 3 , wherein:

the memory controller is further configured to change the third threshold value on the basis of characteristics of a workload of the memory system or a second request from the host device; and

the characteristics of the workload include at least one of the first number, an idle time of the memory system, and an amount of data received from the host device to be written in the nonvolatile memory.

14. The memory system according to claim 6 , wherein:

the memory controller is further configured to change the fourth threshold value on the basis of characteristics of a workload of the memory system or a second request from the host device; and

the characteristics of the workload include at least one of the first number, an idle time of the memory system, and an amount of data received from the host device that has not been written in the nonvolatile memory.

15. The memory system according to claim 7 , wherein:

the memory controller is further configured to change the fifth threshold value on the basis of characteristics of a workload of the memory system or a second request from the host device; and

the characteristics of the workload include at least one of the first number, an idle time of the memory system, and an amount of data received from the host device that has not been written in the nonvolatile memory.

16. The memory system according to claim 8 , wherein:

the memory controller is further configured to change the sixth threshold value on the basis of characteristics of a workload of the memory system or a second request from the host device; and

the characteristics of the workload include at least one of the first number, an idle time of the memory system, and an amount of data received from the host device that has not been written in the nonvolatile memory.

17. The memory system according to claim 1 , wherein the second process includes a program process or an erase process.

18. A memory system comprising:

a nonvolatile memory including a first plane and a second plane; and

a memory controller configured to cause the nonvolatile memory to execute a first process of reading data from the first plane and the second plane in parallel on the basis of a plurality of first requests corresponding to the first plane and a second request corresponding to the second plane,

wherein the memory controller is configured to;

when the first request or the second request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until both of a first number and a second number becomes a first threshold value or more, the first number being a number of the first requests to be performed in the memory controller, the second number being a number of the second requests to be performed in the memory controller, the first threshold value being an integer of 1 or more.

19. The memory system according to claim 18 , wherein

the memory controller is further configured to interrupt the second process when a first period becomes a second threshold value or more while holding the interruption of the second process, and

the first period is a consecutive period during which the first number or the second number is 1 or more.

20. The memory system according to claim 18 , wherein the memory controller is further configured to interrupt the second process when a sum of the first number and the second number becomes a second threshold value or more while holding the interruption of the second process, the second threshold value being an integer of 2 or more.

21. A memory system comprising:

a nonvolatile memory; and

a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device,

wherein the memory controller is configured to:

when the first request is received from the host device while causing the nonvolatile memory to execute a second process, interrupt the second process and cause the nonvolatile memory to execute the first process;

hold resuming of the interrupted second process until a consecutive period during which the second process is being interrupted becomes a threshold value or more; and

resume the interrupted second process in response to the period becoming the threshold value or more.