IP Library Granted Patent US 11,791,267
Granted Patent B2
US 11,791,267 · App. 17/340,584 · Granted Oct 17, 2023

Semiconductor devices

Inventors: Jinho Park (Suwon-si, KR); Shaofeng Ding (Suwon-si, KR); Yongseung Bang (Suwon-si, KR); Jeong Hoon Ahn (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/535H10B12/00
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Quick Facts
Patent No.
US 11,791,267
App. No.
17/340,584
Granted
Oct 17, 2023
Kind
B2
Abstract

A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Claims (61)

1. A semiconductor device, comprising:

a substrate;

a first electrode on the substrate, the first electrode including a first hole;

a first dielectric layer on the first electrode, the first dielectric layer includes a first portion that extends into the first hole;

a second electrode on the first dielectric layer, the second electrode includes a second portion that fills a remainder of the first hole that is not filled by the first portion of the first dielectric layer;

a second dielectric layer on the second electrode;

a third electrode on the second dielectric layer;

a first contact plug extending through and contacting the first electrode and the third electrode;

a second contact plug extending through the second electrode and contacting the second electrode; and

upper wiring layers on each of the first and second contact plugs,

wherein the first contact plug includes

a first part between a lower surface of the first electrode and an upper surface of the substrate,

a second part between an upper surface of the third electrode and the upper wiring layers, and

a third part between an upper surface of the first electrode and a lower surface of the third electrode,

wherein a sidewall of the first part of the first contact plug is offset to a sidewall of the third part of the first contact plug such that a first discontinuous change in a width of the first contact plug is present between the first and third parts of the first contact plug,

wherein the sidewall of the third part of the first contact plug is offset to a sidewall of the second part of the first contact plug such that a second discontinuous change in the width of the first contact plug is present between the second and third parts of the first contact plug,

wherein the second contact plug includes

a first part between an upper surface of the second electrode and the upper wiring layers, and

a second part between a lower surface of the second electrode and the upper surface of the substrate,

wherein a sidewall of the first part of the second contact plug is offset to a sidewall of the second part of the second contact plug,

wherein the second contact plug extends through the first hole such that the second contact plug extends through the first portion of the first dielectric layer and the second portion of the second electrode, and

wherein the first portion of the first dielectric layer contacts the second contact plug.

2. The semiconductor device according to claim 1 , wherein

the second contact plug is isolated from direct contact with the first electrode and the third electrode, and

the second contact plug extends through both the first dielectric layer and the second dielectric layer.

3. The semiconductor device according to claim 1 , wherein

the second contact plug includes

a third part at least partially distal from the upper surface of the substrate in relation to the upper surface of the second electrode, and

a fourth part at least partially between the upper surface of the second electrode and the upper surface of the substrate, and

a sidewall of the third part of the second contact plug is aligned with a sidewall of the fourth part of the second contact plug.

4. A semiconductor device, comprising:

a substrate;

a first electrode on the substrate;

a first dielectric layer on the first electrode;

a second electrode on the first dielectric layer, the second electrode including a first hole;

a second dielectric layer on the second electrode, the second dielectric layer includes a first portion that extends into the first hole;

a third electrode on the second dielectric layer, the third electrode includes a second portion that fills a remainder of the first hole that is not filled by the first portion of the second dielectric layer;

a first contact plug extending through and contacting the first electrode and the third electrode;

an interlayer insulation layer between an upper surface of the substrate and the first electrode;

a first lower wiring layer between the upper surface of the substrate and the interlayer insulation layer; and

upper wiring layers on the first contact plug,

wherein the first contact plug includes

a first part between a lower surface of the first electrode and the upper surface of the substrate,

a second part between an upper surface of the third electrode and the upper wiring layers, and

a third part between an upper surface of the first electrode and a lower surface of the third electrode,

wherein a sidewall of the first part is offset to a sidewall of the third part such that a first discontinuous change in a width of the first contact plug is present between the first and third parts,

wherein the sidewall of the third part is offset to a sidewall of the second part such that a second discontinuous change in the width of the first contact plug is present between the second and third parts,

wherein the first contact plug extends through the interlayer insulation layer and contacts the first lower wiring layer,

wherein the first contact plug extends through the first hole such that the first contact plug extends through the first portion of the second dielectric layer and the second portion of the third electrode, and

wherein the first portion of the second dielectric layer contacts the first contact plug.

5. The semiconductor device according to claim 4 , wherein

the first contact plug is isolated from direct contact with the second electrode, and

the third part of the first contact plug extends through both the first dielectric layer and the second dielectric layer.

6. The semiconductor device according to claim 4 , wherein

the second part of the first contact plug covers a portion of the upper surface of the third electrode, and

the third part of the first contact plug covers a portion of the upper surface of the first electrode.

7. The semiconductor device according to claim 4 , wherein

a width of the second part of the first contact plug is greater than a width of the third part of the first contact plug, and

the width of the third part of the first contact plug is greater than a width of the first part of the first contact plug.

8. The semiconductor device according to claim 4 , further comprising:

a second contact plug extending through the second electrode and contacting the second electrode.

Priority Claims (1)
KR 10-2019-0052419 · May 3, 2019 · national
Continuity (2)
Continuation 16660124 · Oct 22, 2019
Related Publication 20210296229A1 · Sep 23, 2021