Chip package structure

1. A chip package structure, comprising:

a first redistribution structure having a first surface and a second surface opposite to the first surface;

a first chip over the first surface;

a first conductive bump connected between the first chip and the first redistribution structure;

a first conductive pillar over the first surface and electrically connected to the first redistribution structure;

a second chip over the second surface;

a second conductive bump connected between the second chip and the first redistribution structure;

a second conductive pillar over the second surface and electrically connected to the first redistribution structure, wherein the first redistribution structure is between the first conductive pillar and the second conductive pillar;

a first molding layer over the first surface and surrounding the first chip and the first conductive bump, wherein the first conductive pillar is formed in the first molding layer, a first portion of the first molding layer is under a first bottom surface of the first chip, and the first bottom surface faces away from the first redistribution structure; and

a second molding layer over the second surface and surrounding the second chip and the second conductive bump, wherein the second conductive pillar is formed in the second molding layer, a second portion of the second molding layer covers a first top surface of the second chip, the first top surface faces away from the first redistribution structure, and

the first chip, the first redistribution structure, and the second chip are between the first portion of the first molding layer and the second portion of the second molding layer.

2. The chip package structure as claimed in claim 1 , wherein a second bottom surface of the first molding layer is substantially level with a third bottom surface of the first conductive pillar.

3. The chip package structure as claimed in claim 2 , wherein a second top surface of the second molding layer is substantially level with a third top surface of the second conductive pillar.

4. The chip package structure as claimed in claim 1 , wherein the first conductive pillar and the second conductive pillar are arranged in a straight line, and the straight line is perpendicular to the first surface.

5. The chip package structure as claimed in claim 1 , further comprising:

a second redistribution structure over the second chip;

a buffer layer between the second redistribution structure and the second chip; and

a third chip over the second redistribution structure, wherein the second redistribution structure is between the third chip and the buffer layer.

6. The chip package structure as claimed in claim 5 , further comprising:

a third conductive bump passing through the buffer layer and connected between the second conductive pillar and the second redistribution structure.

7. The chip package structure as claimed in claim 3 , wherein the second bottom surface of the first molding layer is lower than the first bottom surface of the first chip.

8. A chip package structure, comprising:

a first redistribution structure having a first surface and a second surface opposite to the first surface;

a first chip over the first surface;

a first conductive bump connected between the first chip and the first redistribution structure;

an interposer over the first surface and electrically connected to the first redistribution structure, wherein the interposer comprises a substrate and a conductive structure passing through the substrate;

a first molding layer over the first surface and surrounding the first chip, the first conductive bump, and the interposer;

a second chip over the second surface;

a second conductive bump connected between the second chip and the first redistribution structure; and

a third conductive bump connected between the interposer and the first redistribution structure.

9. The chip package structure as claimed in claim 8 , wherein a first top surface of the first molding layer and a second top surface of the interposer are substantially level with each other.

10. The chip package structure as claimed in claim 9 , wherein the first top surface of the first molding layer, a third top surface of the substrate, and a fourth top surface of the conductive structure are substantially level with each other.

11. The chip package structure as claimed in claim 8 , further comprising:

a second molding layer over the second surface and surrounding the second chip.

12. The chip package structure as claimed in claim 11 , wherein a first sidewall of the first molding layer and a second sidewall of the second molding layer are substantially coplanar.

13. The chip package structure as claimed in claim 8 , wherein the interposer further comprises a wiring structure between the conductive structure and the first redistribution structure, and the wiring structure is electrically connected to the first redistribution structure and the conductive structure.

14. A chip package structure, comprising:

a redistribution structure comprising a dielectric layer and a wiring structure over and in the dielectric layer, wherein the redistribution structure has a first surface and a second surface opposite to the first surface;

a first chip over the first surface and connected to the wiring structure;

a first conductive pillar over the first surface and connected to the wiring structure;

a second chip over the second surface and connected to the wiring structure;

a second conductive pillar over the second surface and connected to the wiring structure, wherein the redistribution structure is between the first conductive pillar and the second conductive pillar; and

a first molding layer over the first surface and surrounding the first chip, wherein the first conductive pillar is formed in the first molding layer, a first portion of the first molding layer is between the first chip and the redistribution structure and in contact with a third surface of the first chip, and the third surface faces the redistribution structure.

15. The chip package structure as claimed in claim 14 , further comprising:

an adhesive layer over the second chip.

16. The chip package structure as claimed in claim 15 , further comprising:

a second molding layer over the second surface and surrounding the second chip, the adhesive layer and the second conductive pillar.

17. The chip package structure as claimed in claim 16 , wherein a first top surface of the second first molding layer and a second top surface of the adhesive layer are substantially level with each other.

18. The chip package structure as claimed in claim 7 , wherein the second top surface of the second molding layer is higher than the first top surface of the second chip.

19. The chip package structure as claimed in claim 18 , wherein a third portion of the first molding layer is between the first chip and the first redistribution structure, and a fourth portion of the second molding layer is between the second chip and the first redistribution structure.

20. The chip package structure as claimed in claim 16 , wherein the second conductive pillar is formed in the second molding layer, a second portion of the second molding layer is between the second chip and the redistribution structure and in contact with a fourth surface of the second chip, and the fourth surface faces the redistribution structure.