Display panel and display device

1. A display panel, comprising:

a display region;

a light transmitting region at a side of the display region or surrounded by the display region;

a first dummy region between the display region and the light transmitting region, the first dummy region being a non-light emitting region;

a first signal line in the display region and the first dummy region;

a display pixel unit in the display region and comprising a display pixel circuit; and

a first dummy pixel unit in the first dummy region and comprising a first dummy pixel circuit,

wherein the display pixel circuit is connected with the first signal line, and the first dummy pixel circuit is connected with the first signal line,

the display panel further comprises a second signal line and a connection element,

wherein the second signal line has a same extending direction as the first signal line, the second signal line is connected with the first signal line through the connection element, and the second signal line is connected with the first dummy pixel unit,

the display panel further comprises a data line, a light emitting control signal line, a first power line, a second power line, a reset control signal line, a first initialization signal line and a second initialization signal line, wherein the first dummy pixel unit further comprises a dummy element, and the first dummy pixel unit comprises a driving transistor, a data writing transistor, a threshold compensation transistor, a first light emitting control transistor, a second light emitting control transistor, a first reset transistor, a second reset transistor and a storage capacitor,

a first electrode of the storage capacitor is electrically connected with a second electrode of the threshold compensation transistor, and a second electrode of the storage capacitor is electrically connected with the first power line;

a gate electrode of the data writing transistor is electrically connected with the first signal line, and a first electrode and a second electrode of the data writing transistor are respectively electrically connected with the data line and a first electrode of the driving transistor;

a gate electrode of the threshold compensation transistor is electrically connected with the first signal line, a first electrode of the threshold compensation transistor is electrically connected with a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is electrically connected with a gate electrode of the driving transistor;

a gate electrode of the first light emitting control transistor and a gate electrode of the second light emitting control transistor are both connected with the light emitting control signal line;

a first electrode and a second electrode of the first light emitting control transistor are respectively electrically connected with the first power line and the first electrode of the driving transistor, a first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and a second electrode of the dummy element is electrically connected with the second power line;

a gate electrode of the first reset transistor is electrically connected with the reset control signal line, a first electrode of the first reset transistor is electrically connected with the first initialization signal line, and a second electrode of the first reset transistor is electrically connected with the gate electrode of the driving transistor;

a gate electrode of the second reset transistor is electrically connected with the second signal line, and a first electrode of the second reset transistor is electrically connected with the second initialization signal line;

the dummy element is not provided with a first electrode, or in the case where the dummy element is provided with a first electrode, a second electrode of the second light emitting control transistor is not electrically connected with a first electrode of the dummy element, and a second electrode of the second reset transistor is not electrically connected with the first electrode of the dummy element.

2. The display panel according to claim 1 , wherein a structure of the first dummy pixel circuit is the same as a structure of the display pixel circuit.

3. The display panel according to claim 1 , wherein both the display pixel circuit and the first dummy pixel circuit include a transistor.

4. The display panel according to claim 1 , wherein both the display pixel circuit and the first dummy pixel circuit include a storage capacitor.

5. The display panel according to claim 1 , wherein the first signal line comprises a gate line, and the second signal line comprises a reset control signal line.

6. The display panel according to claim 1 , wherein a load formed by the first dummy pixel unit connected with the first signal line is smaller than a load missing from the first signal line before compensation.

7. The display panel according to claim 6 , wherein the load formed by the first dummy pixel unit connected with the first signal line is 65%-80% of the load missing from the first signal line before compensation.

8. The display panel according to claim 1 , further comprising:

a second dummy pixel unit and a second dummy region, wherein the second dummy pixel unit is in the second dummy region, the second dummy region is close to an edge of the display panel and at a side of the first dummy region away from the display region, the second dummy pixel unit comprises a second dummy pixel circuit, and a structure of the second dummy pixel circuit is a part of a structure of the first dummy pixel circuit.

9. The display panel according to claim 1 , wherein a plurality of first signal lines are provided, the plurality of first signal lines extending along a first direction, the plurality of first signal lines are arranged along a second direction, the first direction is intersected with the second direction, and loads of the plurality of first signal lines increase linearly in the second direction.

10. The display panel according to claim 1 , further comprising a notch, wherein the notch is located in the light transmitting region.

11. The display panel according to claim 10 , wherein a plurality of first dummy pixel units are provided, and both ends of the first signal line are connected with the plurality of first dummy pixel units, respectively,

wherein a count of the first dummy pixel units connected with each end of the first signal line is greater than two.

12. The display panel according to claim 11 , wherein the first signal line is on at least one side of two opposite sides of the notch in an extending direction of the first signal line, and a count of the first dummy pixel units connected with one end of the first signal line close to the notch is greater than a count of the first dummy pixel units connected with one end of the first signal line away from the notch.

13. The display panel according to claim 10 , wherein an edge of the display region close to the light transmitting region is a curve, which includes a valley and ridges respectively arranged at both sides of the valley, and the light transmitting region is located at a position of the valley.

14. The display panel according to claim 13 , wherein a slope of a portion of the curve at a side of the ridge close to the notch is greater than a slope of a portion of the curve at a side of the ridge away from the notch.

15. The display panel according to claim 1 , wherein a plurality of first signal lines are provided, the plurality of first signal lines extending along a first direction, the plurality of first signal lines are arranged along a second direction, the first direction is intersected with the second direction, and loads of the plurality of first signal lines decrease linearly and then increase linearly in the second direction.

16. The display panel according to claim 15 , wherein the light transmitting region is surrounded by the display region; the light transmitting region comprises a through hole region, the through hole region comprises a first through hole region and a second through hole region, the first dummy region includes a portion between the first through hole region and the second through hole region, and the first dummy pixel unit is in the portion of the first dummy region between the first through hole region and the second through hole region.

17. The display panel according to claim 1 , further comprising a pixel definition layer, wherein the pixel definition layer is provided with an opening in the display region to define a light emitting area of the display pixel unit, and the pixel definition layer is not provided with an opening in the first dummy region, so that the first dummy pixel unit does not emit light.

18. The display panel according to claim 1 , wherein the first dummy pixel unit further comprises a dummy element, the dummy element is not connected with the first dummy pixel circuit, or a first electrode of the dummy element is not in contact with a light emitting functional layer of the dummy element.