Latency offset for frame-based communications
Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.
1. A method, comprising:
receiving, at a memory device from a host device, a read command and a write command after receiving the read command;
determining, for the read command, a read latency that comprises a first integer quantity of frame periods of a frame clock at the memory device, wherein each frame period comprises a second integer quantity of unit intervals of a first clock;
determining, for the write command, a write latency that comprises a third integer quantity of frame periods of the frame clock greater than the first integer quantity;
determining, for the write command, an offset latency that comprises a fourth integer quantity of unit intervals of the first clock, wherein the fourth integer quantity is less than the second integer quantity of unit intervals in a single frame period of the frame clock; and
writing data associated with the write command at a frame period of the frame clock based at least in part on the write latency and the offset latency.
2. The method of claim 1 , further comprising:
receiving the read command at a first frame period; and
receiving the write command at a second frame period different than the first frame period.
3. The method of claim 2 , further comprising:
aligning the frame clock at the memory device with the first frame period and the second frame period.
4. The method of claim 2 , wherein the second frame period immediately follows the first frame period and the read command and the write command comprise a read-write command.
5. The method of claim 1 , further comprising:
receiving the write data associated with the write command over a data bus between the memory device and the host device.
6. The method of claim 5 , further comprising:
retrieving read data associated with the read command from one or more memory cells of the memory device; and
transmitting, to the host device over the data bus, the read data at a second frame period of the frame clock based at least in part on the read latency.
7. The method of claim 5 , wherein the offset latency is determined as part of a training procedure associated with the data bus.
8. The method of claim 7 , further comprising:
programming the offset latency to a mode register of the memory device based at least in part on the training procedure.
9. The method of claim 1 , wherein the first clock comprises a write clock.
10. The method of claim 1 , wherein the third integer quantity is one number greater than the first integer quantity.
11. The method of claim 1 , further comprising:
retrieving the offset latency from a mode register of the memory device, wherein determining the offset latency is based at least in part on retrieving the offset latency from the mode register.
12. The method of claim 1 , wherein the offset latency comprises a fifth integer quantity of unit intervals of the first clock.
13. A method, comprising:
transmitting, at a host device to a memory device, a read command and a write command after transmitting the read command;
determining, for the read command, a read latency that comprises a first integer quantity of frame periods of a frame clock, wherein each frame period comprises a second integer quantity of unit intervals of a first clock;
determining, for the write command, a write latency that comprises a third integer quantity of frame periods of the frame clock greater than the first integer quantity;
determining, for the write command, an offset latency that comprises a fourth integer quantity of unit intervals of the first clock, wherein the fourth integer quantity is less than the second integer quantity of unit intervals in a single frame period of the frame clock; and
transmitting, to the memory device, write data associated with the write command, wherein the write data is received at a frame period based at least in part on the write latency and the offset latency.
14. The method of claim 13 , further comprising:
transmitting the read command at a first frame period; and
transmitting the write command at a second frame period different than the first frame period.
15. The method of claim 14 , wherein the second frame period immediately follows the first frame period and the read command and the write command comprise a read-write command.
16. The method of claim 13 , wherein the write data associated with the write command is transmitted over a data bus.
17. The method of claim 16 , further comprising:
receiving, from the memory device over the data bus, read data associated with the read command at a second frame period of the frame clock based at least in part on the read latency.
18. The method of claim 16 , wherein the offset latency is determined as part of a training procedure associated with the data bus.
19. The method of claim 13 , wherein the first clock comprises a write clock.
20. The method of claim 13 , wherein the third integer quantity is one number greater than the first integer quantity.
21. The method of claim 13 , wherein the offset latency is retrieved from a mode register of the memory device.
22. The method of claim 13 , wherein the offset latency comprises a fifth integer quantity of unit intervals of the first clock.
23. An apparatus, comprising:
an array of memory cells; and
a controller coupled with the array of
memory cells, the controller configured to cause the apparatus to:
receive, from a host device, a read command and a write command after receiving the read command;
determine, for the read command, a read latency that comprises a first integer quantity of frame periods of a frame clock at the apparatus, wherein each frame period comprises a second integer quantity of unit intervals of a first clock;
determine, for the write command, a write latency that comprises a third integer quantity of frame periods of the frame clock greater than the first integer quantity;
determine, for the write command, an offset latency that comprises a fourth integer quantity of unit intervals of the first clock, wherein the fourth integer quantity is less than the second integer quantity of unit intervals in a single frame period of the frame clock; and
write data associated with the write command received at a frame period of the frame clock based at least in part on the write latency and the offset latency.
24. The apparatus of claim 23 , wherein the controller is further configured to cause the apparatus to:
receive the read command at a first frame period; and
receive the write command at a second frame period different than the first frame period.
25. The apparatus of claim 24 , wherein the controller is further configured to cause the apparatus to:
align the frame clock with the first frame period and the second frame period.
26. The apparatus of claim 24 , wherein the second frame period immediately follows the first frame period and the read command and the write command comprise a read-write command.
27. The apparatus of claim 23 , wherein the controller is further configured to cause the apparatus to:
receive the write data associated with the write command over a data bus between the apparatus and the host device.
28. The apparatus of claim 27 , wherein the controller is further configured to cause the apparatus to:
retrieve read data associated with the read command from one or more memory cells of the array of memory cells; and
transmit, to the host device over the data bus, the read data at a second frame period of the frame clock based at least in part on the read latency.
29. The apparatus of claim 23 , further comprising:
a mode register, wherein the controller is further configured to cause the apparatus to retrieve the offset latency from the mode register, or program the offset latency to the mode register, or both.
30. An apparatus, comprising:
a processor configured to cause the apparatus to:
transmit, to a memory device, a read command and a write command after transmitting the read command;
determine, for the read command, a read latency that comprises a first integer quantity of frame periods of a frame clock, wherein each frame period comprises a second integer quantity of unit intervals of a first clock;
determine, for the write command, a write latency that comprises a third integer quantity of frame periods of the frame clock greater than the first integer quantity;
determine, for the write command, an offset latency that comprises a fourth integer quantity of unit intervals of the first clock, wherein the fourth integer quantity is less than the second integer quantity of unit intervals in a single frame period of the frame clock; and
transmit, to the memory device, write data associated with the write command, wherein the write data is received at a frame period based at least in part on the write latency and the offset latency.
31. The apparatus of claim 30 , wherein the processor is further configured to cause the apparatus to:
transmit the read command at a first frame period; and
transmit the write command at a second frame period different than the first frame period.
32. The apparatus of claim 31 , wherein the second frame period immediately follows the first frame period and the read command and the write command comprise a read-write command.
33. The apparatus of claim 30 , wherein the write data associated with the write command is transmitted over a data bus.
34. The apparatus of claim 33 , wherein the processor is further configured to cause the apparatus to:
receive, from the memory device over the data bus, read data associated with the read command at a second frame period of the frame clock based at least in part on the read latency.
35. A system, comprising:
a host device configured to:
transmit a read command and a write command after transmitting the read command;
determine, for the read command, a read latency that comprises a first integer quantity of frame periods of a frame clock, wherein each frame period comprises a second integer quantity of unit intervals of a first clock;
determine, for the write command, a write latency that comprises a third integer quantity of frame periods of the frame clock greater than the first integer quantity;
determine, for the write command, an offset latency that comprises a fourth integer quantity of unit intervals of the first clock, wherein the fourth integer quantity is less than the second integer quantity of unit intervals in a single frame period of the frame clock; and
transmit write data associated with the write command; and
a memory device comprising a plurality of memory cells and configured to:
receive the read command and the write command after receiving the read command;
determine the read latency for the read command, the write latency for the write command, and the offset latency for the write command; and
receive the write data associated with the write command at a frame period of the frame clock based at least in part on the write latency and the offset latency.