IP Library › Granted Patent US 11,797,196
Granted Patent B2
US 11,797,196 · App. 17/961,048 · Granted Oct 24, 2023

Solid state drive (SSD) and operating method

Inventors: Jung-hyun Hong (Hwaseong-si, KR); Sueng-chul Ryu (Hwaseong-si, KR); Han-min Cho (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F3/0625G06F3/0653G06F3/0659G06F3/0679G11C16/10G11C16/26G11C16/32G11C16/0483
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Quick Facts
Patent No.
US 11,797,196
App. No.
17/961,048
Granted
Oct 24, 2023
Kind
B2
Abstract

A storage system and an operating method thereof are disclosed. The storage system includes a nonvolatile memory that stores data; a computing device to perform data processing on input data provided from the nonvolatile memory or a host outside the storage system; and a controller to control a writing operation and a reading operation of the nonvolatile memory, monitor an operating state of the computing device while the computing device is performing the data processing, and dynamically manage power of the computing device according to a monitoring result.

Claims (31)

1. A solid state drive (SSD), comprising:

a nonvolatile memory including a memory cell array having a three-dimensional (3D) vertical structure in which nonvolatile memory cells are three-dimensionally arranged, to store data received from an external host, wherein the nonvolatile memory is configured with a plurality of chips and a plurality of channels;

an SSD acceleration platform including a plurality of processing elements to perform data processing on input data provided from the nonvolatile memory or the external host by driving an application provided from the external host; and

an SSD controller including a processor, a power manager to adjust power of the SSD acceleration platform, a host interface circuit to transmit a command and data with the external host and to control a writing operation and a reading operation of the nonvolatile memory and an operation of the SSD acceleration platform based on the command, a device interface circuit to communicate with the SSD acceleration platform, and a NAND interface circuit to communicate with the nonvolatile memory,

wherein the SSD controller is configured to:

analyze a characteristic of the application and a data amount of the input data being provided to the SSD acceleration platform for the data processing,

determine an initial hardware utilization of the SSD acceleration platform based on an analysis result,

monitor the hardware utilization of the SSD acceleration platform while the SSD acceleration platform is performing the data processing, and

dynamically perform power management with respect to the SSD acceleration platform based on a monitoring result.

2. The SSD as claimed in claim 1 , wherein the SSD controller is further configured to periodically or aperiodically receive information on at least one of the hardware utilization, a temperature, or a runtime from the SSD acceleration platform, and to dynamically perform the power management with respect to the SSD acceleration platform based on the received information.

3. The SSD as claimed in claim 1 , wherein the SSD controller is further configured to determine, based on a result of the analysis, a number of at least some processing elements that are activated to perform the data processing among the plurality of processing elements included in the SSD acceleration platform.

4. The SSD as claimed in claim 2 , wherein the SSD controller is further configured to adjust at least one of a voltage level of a driving voltage or a frequency of a clock signal based on the received information on the hardware utilization.

5. The SSD as claimed in claim 2 , wherein the SSD controller is further configured to receive real-time temperature information, and dynamically adjust at least one of a voltage level of a driving voltage or a frequency of a clock signal based on the received real-time temperature information.

6. The SSD as claimed in claim 1 , wherein the SSD controller is further configured to adjust at least one of a voltage level of a driving voltage of the SSD acceleration platform or a frequency of a clock signal of the SSD acceleration platform.

7. The SSD as claimed in claim 1 , wherein the SSD controller is further configured to adjust a transmission rate of the input data being transmitted to the SSD acceleration platform to perform the data processing.

8. The SSD as claimed in claim 2 , wherein the SSD controller is further configured to dynamically perform the power management based on the received information and management data pre-configured for the power management of the SSD acceleration platform.

9. The SSD as claimed in claim 8 , wherein the management data includes at least one of a voltage scaling factor of a driving voltage and a frequency scaling factor of a clock signal, the voltage scaling factor and the frequency scaling factor being determined for each of a plurality of values regarding the hardware utilization.

10. The SSD as claimed in claim 1 , wherein the SSD controller is further to receive a data processing result from the SSD acceleration platform after the data processing is finished, and to transmit the data processing result to the external host.

11. The SSD as claimed in claim 1 , wherein the SSD controller is further to control the SSD acceleration platform to be in a low-power state after the data processing is finished.

12. An operating method of a solid state drive (SSD) including a nonvolatile memory including a memory cell array having a three-dimensional (3D) vertical structure in which nonvolatile memory cells are three-dimensionally arranged, to store data received from an external host, wherein the nonvolatile memory is configured with a plurality of chips and a plurality of channels, an SSD acceleration platform including a plurality of processing elements to perform data processing on input data provided from the nonvolatile memory or the external host by driving an application provided from the external host, and an SSD controller including a processor, a power manager to adjust power of the SSD acceleration platform, a host interface circuit to transmit a command and data with the external host and to control a writing operation and a reading operation of the nonvolatile memory and an operation of the SSD acceleration platform based on the command, a device interface circuit to communicate with the SSD acceleration platform, and a NAND interface circuit to communicate with the nonvolatile memory, the operating method comprising:

analyzing a characteristic of the application and a data amount of the input data being provided to the SSD acceleration platform for the data processing,

determining an initial hardware utilization of the SSD acceleration platform based on an analysis result,

monitoring the hardware utilization of the SSD acceleration platform while the SSD acceleration platform is performing the data processing, and

dynamically performing power management with respect to the SSD acceleration platform based on a monitoring result.

13. The operating method as claimed in claim 12 , further comprising:

receiving, by the SSD controller, a data processing result from the SSD acceleration platform after the data processing is finished, and

transmitting, the SSD controller, the data processing result to the external host.

14. The operating method as claimed in claim 12 , further comprising:

switching, by the SSD controller, the SSD acceleration platform to be in a low-power state after the data processing is finished.

15. The operating method as claimed in claim 12 , further comprising:

adjusting, by the SSD controller, a transmission rate of the input data being transmitted to the SSD acceleration platform to perform the data processing.

Priority Claims (1)
KR 10-2018-0157475 · Dec 7, 2018 · national
Continuity (2)
Continuation 16508711 · Jul 11, 2019
Related Publication 20230035828A1 · Feb 2, 2023
Cited By (2)
US 12,619,432 US 12,699,566