IP Library › Granted Patent US 11,798,882
Granted Patent B2
US 11,798,882 · App. 17/135,026 · Granted Oct 24, 2023

Semiconductor package having smart power stage and e-fuse solution

Inventor: Prabal Upadhyaya (San Jose, CA)
Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
H01L23/5256H01L23/31H01L23/49503H01L23/49562H01L23/50H01L23/62H01L27/088H02M3/1582
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Quick Facts
Patent No.
US 11,798,882
App. No.
17/135,026
Granted
Oct 24, 2023
Kind
B2
Abstract

A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

Claims (28)

1. A semiconductor package comprising:

a lead frame comprising

a first die paddle;

a second die paddle; and

an end paddle;

a low side metal-oxide-semiconductor field-effect transistor (MOSFET) being flipped and attached to the first die paddle, the low side MOSFET comprising

a source electrode and a gate electrode on a top surface of the low side MOSFET; and

a drain electrode on a bottom surface of the low side MOSFET;

an E-fuse MOSFET attached to the second die paddle, the E-fuse MOSFET comprising

a source electrode and a gate electrode on a top surface of the E-fuse MOSFET; and

a drain electrode on a bottom surface of the E-fuse MOSFET;

a high side MOSFET attached to the E-fuse MOSFET, the high side MOSFET comprising

a source electrode and a gate electrode on a top surface of the high side MOSFET; and

a drain electrode on a bottom surface of the high side MOSFET, the drain electrode of the high side MOSFET being connected to the source electrode of the E-fuse MOSFET;

a metal connection connecting the drain electrode of the low side MOSFET and the source electrode of the high side MOSFET;

a gate driver integrated circuit (IC) attached to the E-fuse MOSFET;

and

a molding encapsulation enclosing the low side MOSFET, the E-fuse MOSFET, the high side MOSFET, the metal connection, and the gate driver IC.

2. The semiconductor package of claim 1 further comprising an E-fuse IC attached to the gate driver IC; wherein the molding encapsulation further encloses the E-fuse IC.

3. The semiconductor package of claim 1 , wherein a bottom surface of the lead frame is exposed from the molding encapsulation.

4. The semiconductor package of claim 1 , wherein the metal connection is a metal clip electrically and mechanically connected to the drain electrode of the low side MOSFET by a first conductive material;

wherein the metal clip is electrically and mechanically connected to the source electrode of the high side MOSFET by a second conductive material; and

wherein the metal clip is electrically and mechanically connected to the end paddle of the lead frame by a third conductive material.

5. The semiconductor package of claim 4 , wherein each of the first conductive material, the second conductive material, and the third conductive material comprises a solder paste material.

6. The semiconductor package of claim 1 further comprising an E-fuse IC attached to the gate driver IC; wherein the molding encapsulation further encloses the E-fuse IC; wherein the gate driver IC is attached to the E-fuse MOSFET by a first non-conductive material; and wherein the E-fuse IC is attached to the gate driver IC by a second non-conductive material.

7. The semiconductor package of claim 6 , wherein each of the first non-conductive material and the second non-conductive material comprises an epoxy material.

8. The semiconductor package of claim 1 , wherein the gate electrode of the low side MOSFET is connected to an extension portion of the lead frame; and wherein the extension portion of the lead frame extends to an edge of the lead frame.

9. The semiconductor package of claim 8 , wherein one or more bond wires connect the gate driver IC to the extension portion of the lead frame.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2020
From: UPADHYAYA, PRABAL
To: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
Reel/Frame 054754/0676 →
Continuity (1)
Related Publication 20220208656A1 · Jun 30, 2022
Cited By (2)
US 12,535,516 US 12,677,715