IP Library › Granted Patent US 11,799,427
Granted Patent B2
US 11,799,427 · App. 17/514,087 · Granted Oct 24, 2023

Amplifier capacitive load compensation

Inventors: Vishnuvardhan Reddy Jaladanki (Secunderabad, IN); Preetam Charan Anand Tadeparthy (Bengaluru, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03F3/04H02M3/155H03F1/086H03F3/45192H03F3/505H03F2203/45124
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Quick Facts
Patent No.
US 11,799,427
App. No.
17/514,087
Granted
Oct 24, 2023
Kind
B2
Abstract

An amplifier includes a first stage and a second stage. The first stage is configured to amplify a received signal. The second stage is coupled to the first stage. The second stage includes a source follower and a compensation network. The source follower includes an input and an output. The compensation network is coupled to the input of the source follower and the output of the source follower. The compensation network is configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower.

Claims (89)

1. An amplifier, comprising:

a first stage including:

an output;

a first compensation network coupled to the output of the first stage;

a second stage including:

a source follower including:

an input coupled to the output of the first stage; and

an output; and

a second compensation network coupled between the input of the source follower and the output of the source follower;

wherein:

the source follower includes a first transistor having:

a first current terminal coupled to a power supply terminal;

a second current terminal coupled to the second compensation network; and

a control terminal coupled to the output of the first stage; and

the second stage includes:

a second transistor including:

a first current terminal coupled to the first current terminal of the first transistor;

a control terminal coupled to the control terminal of the first transistor; and

a second current terminal; and

a current mirror circuit coupled to the second current terminal of the first transistor and the second current terminal of the second transistor, wherein the current mirror circuit includes:

a third transistor including:

a first current terminal coupled to the second current terminal of the first transistor;

a second current terminal coupled to ground; and

a control terminal; and

a fourth transistor including:

a first current terminal coupled to the second current terminal of the second transistor;

a control terminal coupled to the control terminal of the third transistor; and

a second current terminal coupled to the control terminal of the third transistor.

2. The amplifier of claim 1 , wherein the second compensation network includes:

a resistor including:

a first terminal coupled to the control terminal of the first transistor; and

a second terminal coupled to the second current terminal of the first transistor.

3. The amplifier of claim 2 , wherein the second compensation network includes:

a capacitor including:

a first terminal coupled to the second terminal of the resistor; and

a second terminal coupled to the second current terminal of the first transistor.

4. The amplifier of claim 1 , wherein the source follower includes a current source coupled between the output of the source follower and ground.

5. The amplifier of claim 1 , wherein the first compensation network includes:

a resistor including:

a first terminal coupled to the output of the first stage; and

a second terminal; and

a capacitor including:

a first terminal coupled to the second terminal of the resistor; and

a second terminal coupled to ground.

6. An amplifier, comprising:

a first stage configured to amplify a received signal; and

a second stage coupled to the first stage, and including:

a source follower including an input and an output; and

a compensation network between the input and the output, and configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower;

wherein:

the source follower includes a first transistor including:

a first current terminal coupled to a power supply terminal;

a second current terminal coupled to ground; and

a control terminal coupled to the first stage; and

the second stage includes a second transistor having:

a first current terminal coupled to the power supply terminal;

a second current terminal coupled to ground; and

a control terminal coupled to the control terminal of the first transistor.

7. The amplifier of claim 6 , wherein the compensation network includes a capacitor coupled between the input of the source follower and the output of the source follower.

8. The amplifier of claim 7 , wherein:

the compensation network includes a resistor coupled between the input of the source follower and the output of the source follower; and

the resistor is coupled in series with the capacitor.

9. The amplifier of claim 6 , wherein the source follower includes a current source coupled between the output of the source follower and ground.

10. The amplifier of claim 9 , wherein the second stage includes:

a current mirror circuit having:

a third transistor coupled between the first transistor and ground; and

a fourth transistor coupled between the second transistor and ground.

11. A DC-DC converter comprising:

a controller;

a power stage coupled to the controller, and including:

an amplifier having:

a first stage configured to amplify a received signal; and

a second stage coupled to the first stage, and including:

a source follower, wherein the source follower includes:

an input and an output; and

a first transistor including:

a first current terminal coupled to a power supply terminal;

a second current terminal coupled to ground; and

a control terminal coupled to the first stage;

a compensation network coupled between the input and the output, and configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower; and

a second transistor including:

a first current terminal coupled to the power supply terminal;

a second current terminal coupled to ground; and

a control terminal coupled to the control terminal of the first transistor.

12. The DC-DC converter of claim 11 , wherein the compensation network includes a capacitor and a resistor coupled in series between the input of the source follower and the output of the source follower.

13. The amplifier of claim 11 , wherein the second stage includes:

a current mirror circuit having:

a third transistor coupled between the first transistor and ground; and

a second transistor coupled between the second transistor and ground.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2022
From: JALADANKI, VISHNUVARDHAN REDDY; TADEPARTHY, PREETAM CHARAN ANAND
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 061840/0370 →
Priority Claims (1)
IN 202041049453 · Nov 12, 2020 · national
Continuity (1)
Related Publication 20220149792A1 · May 12, 2022