Fast equalization method, chip, and communications system

1. A fast equalization method, comprising:

storing first equalization parameters that satisfy a link stability requirement and are obtained when an (N−a) th time of link equalization is performed, wherein the first equalization parameters comprise a receive parameter and a transmit parameter of a primary chip and a receive parameter and a transmit parameter of a secondary chip, N≥2, 1≤a<N, and both a and N are integers; and

in response to determining that an N th time of link equalization needs to be performed, reading a first initial fast equalization timeout duration of the primary chip and a second initial fast equalization timeout duration of the secondary chip, wherein the first initial fast equalization timeout duration is less than or equal to an equalization timeout duration that is of the primary chip in a fourth phase of equalization and that exists when the (N−a) th time of link equalization is performed, wherein the second initial fast equalization timeout duration is less than or equal to an equalization timeout duration that is of the secondary chip in a third phase of equalization and that exists when the (N−a) th time of link equalization is performed, wherein both the first and second initial fast equalization timeout durations are device advertised values and are hardware initialized values.

2. The method according to claim 1 , wherein invoking the first equalization parameters comprises:

invoking parameters corresponding to a rate that needs to be reached after the N th time of link equalization is performed and that are in the first equalization parameters, so that the primary chip and the secondary chip perform the N th time of link equalization based on the first fast equalization timeout duration and the parameters corresponding to the rate.

3. The method according to claim 1 , wherein before configuring the first fast equalization timeout duration based on the first and second initial fast equalization timeout durations, the method further comprises:

determining whether the primary chip supports fast equalization; and

determining whether the secondary chip supports the fast equalization; and

wherein configuring the first fast equalization timeout duration comprises:

configuring the first fast equalization timeout duration in response to determining that both the primary chip and the secondary chip support the fast equalization.

4. The method according to claim 3 , wherein determining whether the primary chip supports fast equalization comprises:

when the first initial fast equalization timeout duration is not 0, determining that the primary chip supports the fast equalization.

5. The method according to claim 3 , wherein determining whether the secondary chip supports the fast equalization comprises:

when the second initial fast equalization timeout duration is not 0, determining that the secondary chip supports the fast equalization.

6. The method according to claim 1 , further comprising:

storing second equalization parameters that satisfy the link stability requirement and that are obtained when the Nth time of link equalization is performed, wherein the second equalization parameters comprise the receive parameter and the transmit parameter of the primary chip and the receive parameter and the transmit parameter of the secondary chip.

7. The method according to claim 6 , further comprising:

in response to determining that an (N+b) th time of link equalization needs to be performed, configuring second fast equalization timeout duration; and

invoking the second equalization parameters, so that the primary chip and the secondary chip perform the (N+b) th time of link equalization based on the second fast equalization timeout duration and the second equalization parameters,

wherein the second fast equalization timeout duration represents an equalization timeout duration that is of the primary chip in the third phase of equalization and that exists when the (N+b) th time of link equalization is performed and an equalization timeout duration that is of the primary chip in the fourth phase of equalization and that exists when the (N+b) th time of link equalization is performed, and

wherein the second fast equalization timeout duration represents an equalization timeout duration that is of the secondary chip in the third phase of equalization and that exists when the (N+b) th time of link equalization is performed and an equalization timeout duration that is of the secondary chip in the fourth phase of equalization and that exists when the (N+b) th time of link equalization is performed, the second fast equalization timeout duration is the same as the first fast equalization timeout duration, b≥1, and b is an integer.

8. The method according to claim 1 , wherein after the N th time of link equalization is performed, the method further comprises:

clearing the first fast equalization timeout duration.

9. The method according to claim 1 , wherein the primary chip and the secondary chip are connected to each other via a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus.

10. The method according to claim 1 , further comprising in response to determining that the N th time of link equalization needs to be performed, performing hot reset and link retrain that are triggered by an operating system.

11. The method according to claim 1 , wherein the first initial fast equalization timeout duration is determined based on a physical layer (PHY) capability supported by the primary chip, or the second initial fast equalization timeout duration is determined based on a PHY capability supported by the secondary chip.

12. A fast equalization apparatus, comprising:

one or more processors;

a non-transitory storage medium coupled to the one or more processors and storing instructions for execution by the one or more processors, wherein the instructions, when executed by the one or more processors, configure the apparatus to:

store first equalization parameters that satisfy a link stability requirement and that are obtained when an (N−a) th time of link equalization is performed, wherein the first equalization parameters comprise a receive parameter and a transmit parameter of a primary chip and a receive parameter and a transmit parameter of a secondary chip, N≥2, 1≤a<N, and both a and N are integers;

in response to determining that an N th time of link equalization needs to be performed, read a first initial fast equalization timeout duration of the primary chip and a second initial fast equalization timeout duration of the secondary chip,

wherein the first initial fast equalization timeout duration is less than or equal to equalization timeout duration that is of the primary chip in a fourth phase of equalization and that exists when the (N−a) th time of link equalization is performed,

wherein the second initial fast equalization timeout durations is less than or equal to equalization timeout duration that is of the secondary chip in a third phase of equalization and that exists when the (N−a)th time of link equalization is performed, and

wherein both the first and second initial fast equalization timeout durations are device advertised values and are hardware initialized values.

13. The apparatus according to claim 12 , wherein the instructions, when executed by the one or more processors, configure the apparatus to invoke parameters corresponding to a rate that needs to be reached after the N th time of link equalization is performed and that are in the first equalization parameters, so that the primary chip and the secondary chip perform the N th time of link equalization based on the first fast equalization timeout duration and the parameters corresponding to the rate.

14. The apparatus according to claim 12 , wherein the instructions, when executed by the one or more processors, further configure the apparatus to:

determine whether the primary chip supports fast equalization;

determine whether the secondary chip supports the fast equalization; and

configure the first fast equalization timeout duration when both the primary chip and the secondary chip support the fast equalization.

15. The apparatus according to claim 14 , wherein the primary chip supports the fast equalization when the first initial fast equalization timeout duration is not 0.

16. The apparatus according to claim 14 , wherein the secondary chip supports the fast equalization when the second initial fast equalization timeout duration of the secondary chip is not 0.

17. The apparatus according to claim 12 , wherein the instructions, when executed by the one or more processors, further configure the apparatus to store second equalization parameters that satisfy the link stability requirement and that are obtained when the N th time of link equalization is performed, wherein the second equalization parameters comprise the receive parameter and the transmit parameter of the primary chip and the receive parameter and the transmit parameter of the secondary chip.

18. The apparatus according to claim 17 , wherein the instructions, when executed by the one or more processors, further configure the apparatus to:

in response to determining that an (N+b) th time of link equalization needs to be performed, configure second fast equalization timeout duration; and

invoke the second equalization parameters, so that the primary chip and the secondary chip perform the (N+b) th time of link equalization based on the second fast equalization timeout duration and the second equalization parameters,

wherein the second fast equalization timeout duration represents an equalization timeout duration that is of the primary chip in the third phase of equalization and that exists when the (N+b) th time of link equalization is performed and an equalization timeout duration that is of the primary chip in the fourth phase of equalization and that exists when the (N+b) th time of link equalization is performed, and

wherein the second fast equalization timeout duration represents an equalization timeout duration that is of the secondary chip in the third phase of equalization and that exists when the (N+b) th time of link equalization is performed and an equalization timeout duration that is of the secondary chip in the fourth phase of equalization and that exists when the (N+b) th time of link equalization is performed, the second fast equalization timeout duration is the same as the first fast equalization timeout duration, b≥1, and b is an integer.

19. The apparatus according to claim 12 , wherein the instructions, when executed by the one or more processors, further configure the apparatus to:

after the Nth time of link equalization is performed, clear the first fast equalization timeout duration.

20. A communications system, comprising system software, a primary chip, and a secondary chip connected to each other via a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus; and

wherein the system software, when executed, is adapted to perform a fast equalization method, the method comprising:

storing first equalization parameters that satisfy a link stability requirement and are obtained when an (N−a) th time of link equalization is performed, wherein the first equalization parameters comprise a receive parameter and a transmit parameter of a primary chip and a receive parameter and a transmit parameter of a secondary chip, N≥2, 1≤a<N, and both a and N are integers; and

in response to determining that an N th time of link equalization needs to be performed, reading a first initial fast equalization timeout duration of the primary chip and a second initial fast equalization timeout duration of the secondary chip, wherein the first initial fast equalization timeout duration is less than or equal to an equalization timeout duration that is of the primary chip in a fourth phase of equalization and that exists when the (N−a) th time of link equalization is performed, wherein the second initial fast equalization timeout duration is less than or equal to an equalization timeout duration that is of the secondary chip in a third phase of equalization and that exists when the (N−a) th time of link equalization is performed, wherein both the first and second initial fast equalization timeout durations are device advertised values and are hardware initialized values.