Demodulation reference signal sequence for sidelink communication

1. A method for wireless communication at a first sidelink device, the method comprising:

transmitting a sidelink secondary synchronization sequence based on a first sidelink identifier for the first sidelink device;

transmitting a sidelink primary synchronization sequence based on a second sidelink identifier for the first sidelink device;

determining an initialization parameter based on the first sidelink identifier for the first sidelink device;

determining parameter based on the second sidelink identifier for the first sidelink device;

generating a demodulation reference signal (DMRS) based on the initialization parameter and the at least one scaling parameter; and

transmitting the DMRS to a second sidelink device.

2. The method of claim 1 , wherein generating the DMRS comprises:

initializing a sequence generator with the initialization parameter;

generating a pseudo-random sequence using the sequence generator; and

generating the DMRS from the pseudo-random sequence.

3. The method of claim 2 , wherein determining the initialization parameter is further based on a configured value, a pre-configured value, or a defined value.

4. The method of claim 1 , wherein generating the DMRS comprises:

generating a sequence; and

scaling the sequence with the at least one scaling parameter to generate the DMRS.

5. The method of claim 4 , wherein the at least one scaling parameter comprises a frequency-domain cover code.

6. The method of claim 5 , wherein the frequency-domain cover code is an orthogonal cover code.

7. The method of claim 4 , wherein generating the DMRS comprises:

initializing a sequence generator with the initialization parameter;

generating a pseudo-random sequence using the sequence generator; and

generating the DMRS from the pseudo-random sequence.

8. The method of claim 4 , wherein determining the initialization parameter comprises receiving the initialization parameter via a radio resource control (RRC) message and generating the DMRS comprises:

initializing a sequence generator with the initialization parameter;

generating a pseudo-random sequence using the sequence generator; and

generating the DMRS from the pseudo-random sequence.

9. The method of claim 1 , wherein the at least one scaling parameter comprises a frequency-domain orthogonal cover code (OCC) and generating the DMRS comprises:

initializing a sequence generator with the initialization parameter;

generating a pseudo-random sequence using the sequence generator;

generating a first sequence from the pseudo-random sequence; and

applying the frequency-domain OCC to the first sequence to generate the DMRS.

10. The method of claim 1 , further comprising:

determining a physical layer sidelink synchronization identifier for the first sidelink device based on the first sidelink identifier and the second sidelink identifier.

11. The method of claim 1 , wherein:

the first sidelink identifier is a first value of a set of values from 0 to N; and

the second sidelink identifier is a 0 or a 1.

12. A first sidelink device, comprising:

a transceiver;

a memory; and

a processor communicatively coupled to the transceiver and the memory, wherein the processor and the memory are configured to:

transmit a sidelink secondary synchronization sequence based on a first sidelink identifier for the first sidelink device;

transmit a sidelink primary synchronization sequence based on a second sidelink identifier for the first sidelink device;

determine an initialization parameter based on the first sidelink identifier for the first sidelink device;

determine at least one scaling parameter based on the second sidelink identifier for the first sidelink device;

generate a demodulation reference signal (DMRS) based on the initialization parameter and the at least one scaling parameter; and

transmit the DMRS to a second sidelink device.

13. The first sidelink device of claim 12 , wherein the processor and the memory are further configured to:

initialize a sequence generator with the initialization parameter;

generate a pseudo-random sequence using the sequence generator; and

generate the DMRS from the pseudo-random sequence.

14. The first sidelink device of claim 13 , wherein the processor and the memory are further configured to:

determine the initialization parameter based on a configured value, a pre-configured value, or a defined value.

15. The first sidelink device of claim 12 , wherein the processor and the memory are further configured to:

generate a sequence; and

scale the sequence with the at least one scaling parameter to generate the DMRS.

16. The first sidelink device of claim 15 , wherein the at least one scaling parameter comprises a frequency-domain cover code.

17. The first sidelink device of claim 16 , wherein the frequency-domain cover code is an orthogonal cover code.

18. The first sidelink device of claim 12 , wherein the processor and the memory are further configured to:

initialize a sequence generator with the initialization parameter;

generate a pseudo-random sequence using the sequence generator; and

generate the DMRS from the pseudo-random sequence.

19. The first sidelink device of claim 12 , wherein the processor and the memory are further configured to:

receive the initialization parameter via a radio resource control (RRC) message;

initialize a sequence generator with the initialization parameter;

generate a pseudo-random sequence using the sequence generator; and

generate the DMRS from the pseudo-random sequence.

20. The first sidelink device of claim 12 , wherein the at least one scaling parameter comprises a frequency-domain orthogonal cover code (OCC) and the processor and the memory are further configured to:

initialize a sequence generator with the initialization parameter;

generate a pseudo-random sequence using the sequence generator;

generate a first sequence from the pseudo-random sequence; and

apply the frequency-domain OCC to the first sequence to generate the DMRS.

21. The first sidelink device of claim 12 , wherein the processor and the memory are further configured to:

determine a physical layer sidelink synchronization identifier for the first sidelink device based on the first sidelink identifier and the second sidelink identifier.

22. The first sidelink device of claim 12 , wherein:

the first sidelink identifier is a first value of a set of values from 0 to N; and

the second sidelink identifier is a 0 or a 1.

23. A first sidelink device, comprising:

means for transmitting a sidelink secondary synchronization sequence based on a first sidelink identifier for the first sidelink device;

means for transmitting a sidelink primary synchronization sequence based on a second sidelink identifier for the first sidelink device;

means for determining an initialization parameter based on the first sidelink identifier for the first sidelink device;

means for determining at least one scaling parameter based on the second sidelink identifier for the first sidelink device;

means for generating a demodulation reference signal (DMRS) based on the initialization parameter and the at least one scaling parameter; and

means for transmitting the DMRS to a second sidelink device.

24. The first sidelink device of claim 23 , wherein the means for generating the DMRS comprises:

means for initializing a sequence generator with the initialization parameter;

means for generating a pseudo-random sequence using the sequence generator; and

means for generating the DMRS from the pseudo-random sequence.

25. The first sidelink device of claim 24 , wherein determining the initialization parameter is further based on a configured value, a pre-configured value, or a defined value.

26. The first sidelink device of claim 23 , wherein the means for generating the DMRS comprises:

means for generating a sequence; and

means for scaling the sequence with the at least one scaling parameter to generate the DMRS.

27. The first sidelink device of claim 26 , wherein the at least one scaling parameter comprises a frequency-domain cover code.

28. The first sidelink device of claim 27 , wherein the frequency-domain cover code is an orthogonal cover code.

29. The first sidelink device of claim 23 , further comprising:

means for determining a physical layer sidelink synchronization identifier for the first sidelink device based on the first sidelink identifier and the second sidelink identifier.

30. An article of manufacture for use by a first sidelink device in a wireless communication network, the article of manufacture comprising:

a computer-readable medium having stored therein instructions executable by one or more processors of the first sidelink device to:

transmit a sidelink secondary synchronization sequence based on a first sidelink identifier for the first sidelink device;

transmit a sidelink primary synchronization sequence based on a second sidelink identifier for the first sidelink device;

determine an initialization parameter based on the first sidelink identifier for the first sidelink device;

determine at least one scaling parameter based on the second sidelink identifier for the first sidelink device;

generate a demodulation reference signal (DMRS) based on the initialization parameter and the at least one scaling parameter; and

transmit the DMRS to a second sidelink device.