IP Library › Granted Patent US 11,800,711
Granted Patent B2
US 11,800,711 · App. 17/322,246 · Granted Oct 24, 2023

Integrated assemblies, and methods of forming integrated assemblies

Inventors: Anilkumar Chandolu (Boise, ID); Indra V. Chary (Boise, ID)
Assignee: Micron Technology, Inc.
H10B43/27H10B41/10H10B41/27H10B43/10
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Quick Facts
Patent No.
US 11,800,711
App. No.
17/322,246
Filed
May 17, 2021
Granted
Oct 24, 2023
Kind
B2
Art Unit
2899
USPC
257/314
Abstract

Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

Claims (23)

1. A method of forming an integrated assembly, comprising:

forming laterally alternating first and second strips over a conductive structure, the first strips comprising first sacrificial material and the second strips comprising second sacrificial material;

forming a stack of vertically alternating first levels and insulative second levels over the strips; the first levels comprising first material and the insulative second levels comprising insulative second material;

forming openings to extend through the stack and through at least some of the strips;

forming cell-material-pillars within the openings;

forming slits to extend through the stack and through the strips; the strips extending along a first direction, and the slits extending along a second direction that crosses the first direction;

replacing the first sacrificial material with first conductive material and then replacing the second sacrificial material with second conductive material; and

replacing at least some of the first material of the stack with third conductive material to thereby form the stack to comprise conductive first levels vertically alternating with the insulative second levels.

2. The method of claim 1 wherein one of the first and second sacrificial materials comprises silicon nitride and the other comprises silicon dioxide.

3. The method of claim 1 wherein the first and second strips are about a same lateral thickness as one another.

4. The method of claim 1 wherein the first and second strips are different lateral thicknesses relative to one another.

5. The method of claim 1 further comprising forming insulative panels within the slits.

6. The method of claim 1 wherein the first and second conductive materials comprise conductively-doped semiconductor material.

7. The method of claim 1 wherein the first and second conductive materials comprise conductively-doped silicon.

8. The method of claim 1 wherein the first and second conductive materials comprise silicon doped with one or more n-type dopants.

9. The method of claim 1 wherein the first and second conductive materials are of different compositions relative to one another.

10. The method of claim 1 wherein the first and second conductive materials are of substantially the same composition as one another and join to one another along seams.

11. The method of claim 1 further comprising forming a first layer over the conductive structure prior to forming the alternating strips, and forming a second layer over the alternating strips prior to forming the stack.

12. The method of claim 11 wherein at least one of the first and second layers comprises heavily-doped semiconductor material.

13. The method of claim 11 wherein the first layer is electrically conductive, and wherein the second layer is electrically insulative.

14. The method of claim 1 wherein the cell-material-pillars include channel-material-pillars; wherein the first and second conductive materials comprise heavily-doped semiconductor material and are formed to be directly against the channel-material-pillars; and further comprising out-diffusing dopant from the heavily-doped semiconductor material into the channel-material-pillars, the out-diffused dopant extending upwardly to at least one of the first levels of the stack.

15. The method of claim 14 further comprising forming source-select devices to comprise said at least one of the first levels.

16. The method of claim 1 further comprising forming memory cells along the conductive first levels, with the memory cells comprising regions of the cell-material-pillars; wherein the integrated assembly includes a memory device which comprises the memory cells; and wherein the first and second conductive materials and the conductive structure together form at least a portion of a source structure of the memory device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2021
From: CHANDOLU, ANILKUMAR; CHARY, INDRA V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 056263/0182 →
Continuity (2)
Provisional Application 63072061 · Aug 28, 2020
Related Publication 20220068965A1 · Mar 3, 2022