Pic structure having barrier surrounding opening for optical element to prevent stress damage
A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.
1. A photonic integrated circuit (PIC) structure, comprising:
an active region in at least an active layer over a substrate;
a plurality of dielectric interconnect layers over the active region;
an opening defined through the plurality of dielectric interconnect layers and positioned within the active region, the opening extending to at least the active layer; and
a barrier within the plurality of dielectric interconnect layers and surrounding the opening, the barrier including
a first wall portion meeting a second wall portion at a corner, and
a first buttress wall portion coupling an extension of the first wall portion and the second wall portion.
2. The PIC structure of claim 1 , further comprising a chamfer wall portion spanning between the first wall portion and the second wall portion across the corner.
3. The PIC structure of claim 2 , wherein the barrier further includes:
a second buttress wall portion coupling an extension of the second wall portion and the first wall portion; and
a third buttress wall portion coupling the extension of the first wall portion and the extension of the second wall portion.
4. The PIC structure of claim 1 , wherein the barrier is rectangular and the first wall portion includes a pair of first wall portions and the second wall portion includes an opposing pair of second wall portions, the pair of first wall portions meeting the opposing pair of second wall portions to form four corners, and wherein a chamfer wall portion spans between each first wall portion and a respective second wall portion across each corner.
5. The PIC structure of claim 1 , wherein the barrier further includes a corner buttress including:
the first buttress wall portion coupled to the extension of the first wall portion and the second wall portion;
a second buttress wall portion coupling an extension of the second wall portion and the first wall portion; and
a third buttress wall portion coupling the extension of the first wall portion and the extension of the second wall portion.
6. The PIC structure of claim 5 , wherein the barrier is rectangular and the first wall portion includes a pair of first wall portions and the second wall portion includes an opposing pair of second wall portions, the pair of first wall portions meeting the opposing pair of second wall portions to form four corners, and wherein a corner buttress is positioned at each corner.
7. The PIC structure of claim 1 , wherein the opening includes a plurality of openings defined within the plurality of dielectric interconnect layers and positioned within the active region, each opening extending to at least the active layer, and wherein the barrier within the plurality of dielectric interconnect layers surrounds each opening, and
further comprising an optical element positioned within each opening.
8. The PIC structure of claim 1 , wherein the barrier includes a plurality of interconnected wire and via layers; and
a plurality of anchors coupled to a lowermost one of the plurality of interconnected wires and via layers, and extending at least into the substrate.
9. The PIC structure of claim 1 , further comprising:
an optical element positioned in the opening; and
a waveguide extending laterally through the barrier, the waveguide configured to optically communicate between the optical element and a component in at least one of the plurality of interconnect layers, the active layer and the substrate.
10. The PIC structure of claim 1 , further comprising a crack stop ring extending about an outer periphery of the PIC structure, and the crack stop ring positioned outside of the active region.
11. A photonic integrated circuit (PIC) structure, comprising:
an active region in at least an active layer over a substrate;
a plurality of dielectric interconnect layers over the active region;
an opening defined through the plurality of interconnect layers and positioned within the active region, the opening extending to at least the active layer; and
a barrier within the plurality of dielectric interconnect layers and surrounding the opening;
wherein the barrier includes:
a first wall portion meeting a second wall portion at a corner,
a first buttress wall portion coupling an extension of the first wall portion and the second wall portion, and
a chamfer wall portion spanning between the first wall portion and the second wall portion across the corner.
12. The PIC structure of claim 11 , wherein the barrier further includes a corner buttress:
the first buttress wall portion coupled to the extension of the first wall portion and the second wall portion;
a second buttress wall portion coupling an extension of the second wall portion and the first wall portion; and
a third buttress wall portion coupling the extension of the first wall portion and the extension of the second wall portion.
13. The PIC structure of claim 11 , wherein the barrier includes a plurality of interconnected wire and via layers; and
a plurality of anchors coupled to a lowermost one of the plurality of interconnected wires and via layers, and extending at least into the substrate.
14. The PIC structure of claim 11 , further comprising a crack stop ring extending about an outer periphery of the PIC structure, the crack stop ring positioned outside of the active region.
15. The PIC structure of claim 11 , further comprising:
an optical element positioned in the opening; and
a waveguide extending laterally through the barrier, the waveguide configured to optically communicate between the optical element and a component in at least one of the plurality of interconnect layers, the active layer and the substrate.
16. A method, comprising:
forming a barrier with a plurality of dielectric interconnect layers over an active layer of an active region of a photonics integrated circuit (PIC) structure, the barrier surrounding a reserved area within the active region;
forming an opening in the reserved area and through the plurality of dielectric interconnect layers to at least the active layer of the active region; and
wherein the barrier includes:
a first wall portion meeting a second wall portion at a corner,
a first buttress wall portion coupling an extension of the first wall portion and the second wall portion, and
a chamfer wall portion spanning between the first wall portion and the second wall portion across the corner.
17. The method of claim 16 , wherein forming the barrier further includes forming a corner buttress including:
forming the first buttress wall portion coupling the extension of the first wall portion and the second wall portion;
forming a second buttress wall portion coupling an extension of the second wall portion and the first wall portion; and
forming a third buttress wall portion coupling the extension of the first wall portion and the extension of the second wall portion.
18. The method of claim 16 , wherein forming the opening includes forming a plurality of openings defined within the plurality of dielectric interconnect layers and positioned within the active region, each opening extending to at least the active layer, and wherein the barrier within the plurality of dielectric interconnect layers surrounds each opening, and
further comprising coupling an optical element within each opening.
19. The method of claim 16 , further comprising coupling an optical element in the opening.
20. The method of claim 16 , further comprising, during forming the barrier, forming a crack stop ring extending along an outer periphery of the PIC structure, and positioned outside of an outer extent of the active region.