Semiconductor devices
A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
1. A semiconductor device, comprising:
active fins protruding on an upper surface of a substrate;
a first isolation pattern on the upper surface of the substrate, the first isolation pattern extending on respective lower sidewalls of the active fins;
a third isolation pattern extending into the first isolation pattern; and
a second isolation pattern in a trench extending into the upper surface of the substrate, the trench having a cross-section of an at least partially circular shape or an at least partially elliptical shape, the second isolation pattern comprising:
an upper portion contacting the third isolation pattern and comprising a substantially planar surface; and
a lower portion extending in the trench, the lower portion contacting the upper portion of the second isolation pattern.
2. The semiconductor device of claim 1 , wherein the active fins extend in a first direction substantially parallel to the upper surface of the substrate, and the active fins are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and intersecting with the first direction,
wherein an isolation structure comprising the second and third isolation patterns extends in the first direction, and
wherein the first isolation pattern laterally extends along the upper surface of the substrate adjacent to the trench.
3. The semiconductor device of claim 1 , wherein the upper portion of the second isolation pattern has a convex surface contacting the third isolation pattern.
4. The semiconductor device of claim 1 , wherein a sidewall of the lower portion of the second isolation pattern has a varying slope with respect to the upper surface of the substrate.
5. The semiconductor device of claim 1 , wherein a width of the lower portion of the second isolation pattern increases from a top portion to a central portion, and decreases from the central portion to a bottom portion.
6. The semiconductor device of claim 1 , wherein the second isolation pattern comprises a nitride, and the third isolation pattern comprises an oxide.
7. The semiconductor device of claim 1 , wherein sidewalls of the first isolation pattern are free of the second isolation pattern.
8. A semiconductor device, comprising:
active fins protruding on an upper surface of a substrate;
a first isolation pattern on the upper surface of the substrate, the first isolation pattern extending on respective lower sidewalls of the active fins;
a second isolation pattern in a trench extending into the upper surface of the substrate, the second isolation pattern having surfaces that are curved along a first direction substantially parallel to the upper surface of the substrate; and
a third isolation pattern extending into the first isolation pattern, the third isolation pattern having a surface that is curved along the first direction,
wherein an upper surface of the second isolation pattern contacts a lower surface of the third isolation pattern and comprises a substantially planar surface, and a lower surface of the second isolation pattern contacts the substrate.
9. The semiconductor device of claim 8 , wherein a central portion in the first direction of the second isolation pattern has an upper surface higher than that an edge portion in the first direction of the second isolation pattern.
10. The semiconductor device of claim 8 , wherein a sidewall of an edge portion of the second isolation pattern has a varying slope with respect to the upper surface of the substrate.
11. The semiconductor device of claim 10 , wherein a width of the second isolation pattern increases from an upper portion to a central portion, and decreases from the central portion to a lower portion.
12. The semiconductor device of claim 10 , wherein the second isolation pattern comprises a nitride, and the third isolation pattern comprises an oxide.
13. The semiconductor device of claim 8 , wherein the active fins extend in a second direction substantially parallel to the upper surface of the substrate and intersecting with the first direction, and the active fins are spaced apart from each other in the first direction,
wherein an isolation structure comprising the second and third isolation patterns extends in the second direction, and
wherein the first isolation pattern laterally extends along the upper surface of the substrate adjacent to the trench.
14. The semiconductor device of claim 8 , wherein the second isolation pattern has a cross-section of an at least partially circular shape or an at least partially elliptical shape.
15. A semiconductor device, comprising:
active fins protruding on an upper surface of a substrate;
a first isolation pattern on the upper surface of the substrate, the first isolation pattern extending on respective lower sidewalls of the active fins;
a third isolation pattern extending into the first isolation pattern; and
a second isolation pattern in a trench extending into the upper surface of the substrate, the trench having a cross-section of an at least partially circular shape or an at least partially elliptical shape, the second isolation pattern comprising:
an upper portion contacting the third isolation pattern and comprising a substantially planar surface; and
a lower portion extending in the trench, the lower portion contacting the upper portion of the second isolation pattern;
a gate structure on the active fins; and
a source/drain layer on the substrate adjacent to the gate structure.
16. The semiconductor device of claim 15 , wherein the active fins extend in a first direction substantially parallel to the upper surface of the substrate, and the active fins are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and intersecting with the first direction,
wherein an isolation structure comprising the second and third isolation patterns extends in the first direction, and
wherein the first isolation pattern laterally extends along the upper surface of the substrate adjacent to the trench.
17. The semiconductor device of claim 15 , wherein the second isolation pattern comprises a nitride, and the third isolation pattern comprises an oxide.