Transition metal dichalcogenide transistor and preparation method thereof

1. A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties.

2. The transition metal dichalcogenide transistor of claim 1 , wherein the first transition metal dichalcogenide is at least one of MoTe 2 , MoS 2 and WTe 2 .

3. The transition metal dichalcogenide transistor of claim 1 , wherein the second transition metal dichalcogenide is at least one of MoTe 2 , MoS 2 , MoSe 2 , WSe 2 , ReSe 2 , TaS 2 , TaSe 2 , TaTe 2 , NbS 2 , NbSe 2 and NbTe 2 .

4. The transition metal dichalcogenide transistor of claim 1 , wherein center points of the channel layer, the gate dielectric layer and the gate are located on the same straight line.

5. The transition metal dichalcogenide transistor of claim 1 , wherein further comprising an adhesion layer, which is between the gate dielectric layer and the channel layer, and in the plane paralleled to the channel layer, the length of the adhesion layer in each direction is equal to the length of the gate dielectric layer; the source region and the drain region of the source/drain region are located respectively on both the sides of the gate dielectric layer and the adhesive layer.

6. The transition metal dichalcogenide transistor of claim 5 , wherein the adhesion layer is lattice-matched with the second transition metal dichalcogenide.

7. A preparation method for a transition metal dichalcogenide transistor of claim 5 , comprising: S 01 : providing a substrate, forming the interlayer dielectric layer on the substrate, and forming a groove on the upper surface of the interlayer dielectric layer;

S 02 : filling a gate material in the groove of the interlayer dielectric layer to form the gate;

S 03 : forming a gate dielectric layer and an adhesion layer in sequence above the gate;

wherein, in a plane paralleled to the channel layer, the length of the adhesion layer in each direction is equal to the length of the gate dielectric, and both lengths are greater than or equal to the length of the gate; the source region and the drain region are respectively located on both the sides of the gate dielectric layer and the adhesion layer;

S 04 : depositing the first transition metal dichalcogenide with metallic properties on the upper surfaces both of the adhesion layer and the interlayer dielectric layer, and removing the first transition metal dichalcogenide on the upper surface of the adhesion layer by photo-lithography and etching, and then doping to form the source/drain region on both the sides of the gate dielectric layer and the adhesion layer;

S 05 : depositing the passivation layer on the upper surfaces both of the source/drain region and the adhesion layer, forming a groove on the upper surface of the adhesion layer by etching, and filling the groove with the second transition metal dichalcogenide with semiconductor properties to form the channel layer; wherein, in the plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the lengths both of the gate dielectric layer and the adhesion layer;

S 06 : forming extraction electrodes in the passivation layer and respectively connected with the source/drain region.

8. The method of claim 7 , wherein, for the source/drain region of NMOS, doping elements in the step S 04 is one or more of As, P, and C; for the source/drain region of PMOS, the doping elements in the step S 04 is B and/or Ge.

9. The transition metal dichalcogenide transistor of claim 1 , wherein the heights of the source/drain region are greater than or equal to the height of the gate dielectric layer.

10. A preparation method for a transition metal dichalcogenide transistor of claim 1 , comprising: S 01 : providing a substrate, forming the interlayer dielectric layer on the substrate, and forming a groove on the upper surface of the interlayer dielectric layer;

S 02 : filling a gate material in the groove of the interlayer dielectric layer to form the gate;

S 03 : forming the gate dielectric layer above the gate, wherein, in the plane paralleled to the channel layer, the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate;

S 04 : depositing the first transition metal dichalcogenide with metallic properties on the upper surfaces both of the gate dielectric layer and the interlayer dielectric layer, and removing the first transition metal dichalcogenide on the upper surface of the gate dielectric layer by photo-lithography and etching, and then doping to form the source/drain region on both the sides of the gate dielectric layer;

S 05 : depositing the passivation layer on the upper surfaces both of the source/drain region and the gate dielectric layer, forming a groove on the upper surface of the gate dielectric layer by etching, and filling the groove with the second transition metal dichalcogenide with semiconductor properties to form the channel layer; wherein, in the plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer;

S 06 : forming extraction electrodes in the passivation layer and respectively connected with the source/drain region.

11. The method of claim 10 , wherein, for the source/drain region of NMOS, doping elements in the step S 04 is one or more of As, P, and C; for the source/drain region of PMOS, the doping elements in the step S 04 is B and/or Ge.