IP Library Granted Patent US 11,804,574
Granted Patent B2
US 11,804,574 · App. 17/393,852 · Granted Oct 31, 2023

Streamlined GaN-based fabrication of light emitting diode structures

Inventors: Richard J. Brown (Ithaca, NY); Christopher M. Martin (Ithaca, NY); Shikhar Bajracharya (Ithaca, NY)
Assignee: Odyssey Semiconductor, Inc.
H01L33/32H01L27/153H01L27/156H01L33/0075H01L33/382H01L33/40
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Quick Facts
Patent No.
US 11,804,574
App. No.
17/393,852
Granted
Oct 31, 2023
Kind
B2
Abstract

Light Emitting Diodes (LEDs) made with GaN and related materials are used to realize high efficiency devices which emit visible radiation. These GaN-based LEDs consists of a multi-layer structure which include p-type electron confinement layers, and p-type current spreading and ohmic contacts layers located above the active region. The alignment of the etched features which penetrate near or through the active region and the ohmic contact is critical and is currently a technological challenge in the fabrication process. Any errors in this alignment and successive layers will short across the active layers of the device and result in reduced yield of functional devices. The invention described herein provides a method and apparatus to realize the successful alignment and streamlined fabrication of high-density LED array devices. The result is a higher pixel density GaN-based LED device with higher current handling capability resulting in a brighter device of the same area.

Claims (19)

1. A microLED array device, the device comprising:

a substrate member comprising a surface region;

an n-type gallium nitride material formed overlying the surface region;

an active layer formed overlying the n-type gallium nitride material, the active layer having a predetermined thickness;

a p-type gallium nitride material formed overlying the active layer to form a stack including the n-type gallium nitride material, the active layer, and the p-type gallium nitride material;

a plurality of p-type contact regions formed overlying the p-type gallium nitride material, each of the p-type contact regions having an ohmic contact region, the plurality of p-type contact regions being configured as an N by M array, such that each of the p-type contact regions has a size of a pixel element;

a plurality of the pixel elements formed from the p-type contact regions and the stack, wherein each of the pixel elements is separated from each other;

a trench region formed within the stack to expose a portion of the n-type gallium nitride material; and

an n-type contact region formed within the trench region comprising a metal fill material overlying an exposed portion of the n-type gallium nitride material; and

wherein the n-type contact region is characterized by a same height as an upper surface of the p type contact regions.

2. The device of claim 1 , wherein the n-type contact regions are configured as a cathode; and each of the p-type contact regions forms an anode for each of the pixel elements; wherein the p-type gallium nitride material comprises a magnesium impurity; and the n-type gallium nitride material comprises a silicon impurity.

3. The device of claim 1 , wherein the n-type contact region is an ohmic contact to the n-type gallium nitride material.

4. The device of claim 1 , wherein each of the p-type contact regions is configured as a bump bondable pad.

5. The device of claim 1 , wherein the n-type contact region provided in the n-type contact frame serves as a sheet contact to form an anode for each pixel element.

6. The device of claim 1 , further comprising a conformal passivation layer formed overlying a surface region of a plurality of exposed regions of the plurality of pixel elements; wherein the portions of conformal passivation layer overlying each of the p-type contact regions and the portion of the conformal passivation layer overlying the upper region of the n-type contact region are removed to expose each of the p-type contact regions and expose the n-type contact region.

7. The device of claim 1 , wherein the array has a size of about five millimeters to about fifty millimeters along a length of the array.

8. The device of claim 1 , wherein the metal fill comprises a titanium entity and a gold entity.

9. The device of claim 1 , wherein each pixel element is self-aligned.

10. The device of claim 1 , wherein the array has an electrical yield of greater than 99.5% or greater.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2024
From: ODYSSEY SEMICONDUCTOR, INC.
To: POWER INTEGRATIONS, INC.
Reel/Frame 067887/0113 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2021
From: BROWN, RICHARD J.; MARTIN, CHRISTOPHER M.; BAJRACHARYA, SHIKHAR
To: ODYSSEY SEMICONDUCTOR, INC.
Reel/Frame 057091/0925 →
Continuity (3)
Division 16813362 · Mar 9, 2020
Provisional Application 62981268 · Feb 25, 2020
Related Publication 20210367107A1 · Nov 25, 2021