Methods and apparatus to implement compensation circuitry in an envelope detector

1. An apparatus comprising:

a compensation circuit including:

a current compensation output;

a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output; and

a resistor ladder with a tap terminal coupled to the first control terminal;

a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output; and

a rectification circuit having an input coupled to the mirror output.

2. The apparatus of claim 1 , wherein the compensation circuit includes a bias circuit coupled to the first control terminal through the resistor ladder, and a plurality of transistors include the first transistor.

3. The apparatus of claim 2 , wherein the resistor ladder includes a plurality of resistor branches and a plurality of tap terminals, and each transistor of the plurality of transistors includes a control terminal coupled to a tap terminal.

4. The apparatus of claim 1 , wherein the resistor ladder is configurable to a linear compensation configuration or a sinusoidal compensation configuration, the sinusoidal compensation configuration enables the tap terminals that generate a sinusoidal compensation signal.

5. The apparatus of claim 1 , wherein the compensation circuit further including:

the resistor ladder being a first resistor ladder and a second resistor ladder; and

a second transistor including a second control terminal and a second current terminal, the second control terminal coupled to a bias circuit through the second resistor ladder, the second current terminal coupled to the current compensation output.

6. The apparatus of claim 1 , wherein the compensation circuit further coupled to an adjustment current source and a bias current source, and a current from the adjustment current source is based on an on-off keying modulated carrier signal received by the rectification circuit.

7. The apparatus of claim 1 , wherein rectification circuit includes a primary transistor and a secondary transistor, the primary and the secondary transistors configured to receive the on-off keying modulated carrier signal and a current from the mirror output.

8. The apparatus of claim 7 , wherein the current from the mirror output is a scaled version of an average sum of currents flowing through the primary transistor and the secondary transistor.

9. The apparatus of claim 1 , wherein the rectification circuit is coupled to an output stage including an input and an output, the input coupled to the rectification circuit and the mirror output, and the output configured to generate a digital signal output.