Shared memory for intelligent network interface cards
In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
1. A network interface, comprising:
a hardware bus interface circuit to communicatively couple the network interface to a host computer, wherein the host computer has a central processor unit (CPU);
a memory circuit comprising a shareable memory region that can be cache coherently mapped to an address space of the host computer;
a coprocessor circuit to provide an accelerated network support function via the shareable memory region; and
a caching agent (CA) circuit to maintain cache coherency between the coprocessor and the CPU via the shareable memory region.
2. The network interface of claim 1 , wherein the network support function comprises encryption.
3. The network interface of claim 1 , wherein the network support function comprises decryption.
4. The network interface of claim 1 , wherein the network support function comprises compression.
5. The network interface of claim 1 , wherein the network support function comprises decompression.
6. The network interface of claim 1 , wherein the network support function comprises internet protocol security.
7. The network interface of claim 1 , further comprising a bus interface to communicatively couple to the host computer.
8. The network interface of claim 7 , wherein bus interface is a peripheral component interconnect express (PCIe) interface.
9. The network interface of claim 1 , wherein the CA circuit is to coherently handle a memory write from the host computer to the shareable memory region.
10. The network interface of claim 1 , wherein the CA circuit is to coherently handle a memory read from the shareable memory region to the host computer.
11. One or more non-transitory computer-readable media having stored thereon executable instructions to:
map a local memory location of a memory address space of a host device having a first caching agent (CA) to a memory region of a network interface having a second CA, wherein the network interface comprises a coprocessor circuit to provide an accelerated network support function that uses the memory region;
instruct the coprocessor circuit to perform the accelerated network support function;
write a first datum to the local memory location, comprising maintaining cache coherency between the memory address space and the memory region of the network interface; and
read a second datum from the local memory location, comprising maintaining cache coherency between the memory address space and the memory region of the network interface.
12. The one or more non-transitory computer-readable media of claim 11 , wherein the network support function comprises encryption and/or decryption.
13. The one or more non-transitory computer-readable media of claim 11 , wherein the network support function comprises compression and/or decompression.
14. The one or more non-transitory computer-readable media of claim 11 , wherein the network support function comprises a security function.
15. The one or more non-transitory computer-readable media of claim 11 , wherein the executable instructions are further to communicate with the network interface via a peripheral component interconnect express (PCIe) bus.
16. A computing apparatus comprising:
a local host comprising a processor circuit and a host memory addressable via an address space and a first caching agent (CA);
a network interface, comprising a coprocessor circuit to perform a network support function, a network interface memory comprising a region accessible by the coprocessor circuit, and a second CA;
a communication bus to communicatively couple the network interface to the processor circuit; and
a software driver for the network interface, comprising instructions encoded within the host memory to instruct the processor circuit to:
map the region of the network interface memory to a location of the host memory;
instruct the coprocessor circuit to carry out the network support function; and
maintain read and write cache coherency between the region accessible by the coprocessor circuit and the location of the host memory.
17. The computing apparatus of claim 16 , wherein the communication bus is a peripheral component interconnect express (PCIe) bus.
18. The computing apparatus of claim 16 , wherein the coprocessor circuit is an application-specific integrated circuit.
19. The computing apparatus of claim 16 , wherein the coprocessor circuit comprises a field-programmable gate array.
20. The computing apparatus of claim 16 , wherein the coprocessor circuit comprises an intellectual property block.
21. The computing apparatus of claim 16 , wherein the network support function comprises encryption.
22. The computing apparatus of claim 16 , wherein the network support function comprises decryption.
23. The computing apparatus of claim 16 , wherein the network support function comprises compression and/or decompression.
24. The computing apparatus of claim 16 , wherein the network support function comprises a security function.
25. The computing apparatus of claim 16 , wherein the communication bus is a peripheral component interconnect express (PCIe) bus.