Transporting request types with different latencies

1. A memory-compute node comprising:

a hybrid threading processor;

a memory controller;

a fabric interface; and

a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller,

wherein the fabric interface supports a first virtual channel (VC0) and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to a scale fabric, and

wherein the fabric interface configured to:

receive, from the hybrid threading processor, a first message that includes a memory request to a destination memory controller, on the second virtual channel over the NOC; and

transmit the first message to the destination memory controller across the scale fabric via the first virtual channel or the third virtual channel depending on a latency characteristic of the first message.

2. The memory-compute node of claim 1 , wherein the memory-compute node is one of a plurality of memory-compute nodes coupled to one another over the scale fabric.

3. The memory-compute node of claim 1 , wherein to transmit the first message to the destination memory controller, the fabric interface is configured to:

determine that the first message is a short latency memory request for a destination memory controller across the scale fabric; and

in response to determining that the first message is a short latency memory request, transmit the first message toward the destination memory controller on the first virtual channel over the scale fabric.

4. The memory-compute node of claim 3 , wherein to determine that the first message is the short latency memory request, the fabric interface is to decode a packet header and determine that the first message is the short latency memory request based on the packet header.

5. The memory-compute node of claim 1 , wherein to transmit the first message to the destination memory controller, the fabric interface is configured to:

determine that the first message is a long latency memory request for the destination memory controller; and

in response to determining that the first message is a long latency memory request, transmit the first message toward the destination memory controller on the third virtual channel over the scale fabric.

6. A system comprising:

multiple memory-compute nodes coupled to one another over a scale fabric, wherein each memory-compute node comprises:

a hybrid threading processor;

a memory controller;

a fabric interface; and

a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller,

wherein the fabric interface supports a first plurality of virtual channels to the NOC, a second plurality of virtual channels to the scale fabric, and a common virtual channel between the first plurality of virtual channels and the second plurality of virtual channels, and

wherein the fabric interface configured to:

receive, from the hybrid threading processor, a first message that includes a memory request to a destination memory controller, on the common virtual channel over the NOC; and

transmit the first message to the destination memory controller across the scale fabric via a first virtual channel or a second virtual channel of the second plurality of virtual channels, depending on a latency characteristic of the first message.

7. The system of claim 6 , wherein the memory-compute node is one of a plurality of memory-compute nodes coupled to one another over the scale fabric.

8. The system of claim 6 , wherein to transmit the first message to the destination memory controller, the fabric interface is configured to:

determine that the first message is a short latency memory request for a destination memory controller across the scale fabric; and

in response to determining that the first message is a short latency memory request, transmit the first message toward the destination memory controller on the first virtual channel over the scale fabric.

9. The system of claim 8 , wherein to determine that the first message is the short latency memory request, the fabric interface is to decode a packet header and determine that the first message is the short latency memory request based on the packet header.

10. The system of claim 9 , wherein the packet header includes a command field, and wherein short latency memory requests are associated with a subset of commands indicated in the command field.

11. The system of claim 6 , wherein to transmit the first message to the destination memory controller, the fabric interface is configured to:

determine that the first message is a long latency memory request for the destination memory controller; and

in response to determining that the first message is a long latency memory request, transmit the first message toward the destination memory controller on the second virtual channel over the scale fabric.

12. The system of claim 11 , wherein the long latency memory request includes a custom atomic operation.

13. The system of claim 6 , wherein the fabric interface is to:

receive a response to the first message from the destination memory controller; and

relay the response to the hybrid threading processor.

14. The system of claim 13 , wherein the hybrid threading processor is to, prior to sending the first message to the fabric interface:

determine based on a credit counter whether a credit is available to transmit the first message toward the destination memory controller, the credit issued by the destination memory controller; and

decrement the credit counter based on sending the first message.

15. The system of claim 14 , wherein the credit is a short latency credit.

16. The system of claim 14 , wherein the credit is a long latency credit.

17. The system of claim 13 , wherein the fabric interface is to:

transmit a credit to the hybrid threading processor after transmitting the first message toward the destination memory controller, the credit to allow the hybrid threading processor to send another message to the destination memory controller.

18. The system of claim 17 , wherein the hybrid threading processor is to, after receiving the credit from the fabric interface:

update a credit counter based on the credit.

19. A method comprising:

receiving, at a fabric interface that supports a first plurality of virtual channels to a network on chip (NOC), a second plurality of virtual channels to a scale fabric, and a shared virtual channel between the first plurality of virtual channels and the second plurality of virtual channels, from a hybrid threading processor that is coupled to the fabric interface, a first message that includes a memory request to a destination memory controller, on the shared virtual channel over the NOC; and

transmitting the first message to the destination memory controller across the scale fabric via a first virtual channel or a second virtual channel of the second plurality of virtual channels, depending on a latency characteristic of the first message.

20. The method of claim 19 , wherein transmitting the first message comprises:

determining that the first message is a short latency memory request for a destination memory controller across the scale fabric; and

in response to determining that the first message is a short latency memory request, transmitting the first message toward the destination memory controller on the first virtual channel over the scale fabric.

21. The method of claim 20 , wherein determining that the first message is the short latency memory request comprises decoding a packet header and determining that the first message is the short latency memory request based on the packet header.

22. The method of claim 21 , wherein the packet header includes a command field, and wherein short latency memory requests are associated with a subset of commands indicated in the command field.

23. The method of claim 19 , wherein transmitting the first message comprises:

determining that the first message is a long latency memory request for the destination memory controller; and

in response to determining that the first message is a long latency memory request, transmitting the first message toward the destination memory controller on the second virtual channel over the scale fabric.

24. The method of claim 23 , wherein the long latency memory request includes a custom atomic operation.

25. A non-transitory machine-readable medium including instructions, which when executed by a machine, cause the machine to perform operations comprising:

receiving, at a fabric interface that supports a first plurality of virtual channels to a network on chip (NOC), a second plurality of virtual channels to a scale fabric, and a common virtual channel between the first plurality of virtual channels and the second plurality of virtual channels, from a hybrid threading processor that is coupled to the fabric interface, a first message that includes a memory request to a destination memory controller on the common virtual channel over the NOC; and

transmitting the first message to the destination memory controller across the scale fabric via a first virtual channel or a second virtual channel of the second plurality of virtual channels, depending on a latency characteristic of the first message.