Controller in high-speed SPI master mode
View Patent ↗In view of defects in the prior art, the present disclosure provides a controller in a high-speed serial peripheral interface (SPI) master mode, where clock signals are provided by a phase locked loop (PLL), and the entire controller includes: a low-speed clock domain and a high-speed clock domain, where the PLL provides two main clock signals by different clock frequency dividers, provides a low-speed clock signal to the low-speed clock domain, and provides a high-speed source clock signal to the high-speed clock domain. By such technical solutions in the present disclosure, functions of different clock domains are divided through asynchronization of a high-speed SPI controller, and the function of a high-speed SPI flash access is implemented, thereby saving a read/write time. Especially in an application scenario of an SPI flash boot, the controller can greatly optimize a startup time.
1. A controller in a high-speed serial peripheral interface (SPI) master mode, wherein clock signals are provided by a phase locked loop (PLL), and the controller comprises:
a low-speed clock domain, comprising a direct memory access (DMA) control interface, used for data interaction between the controller and a memory, and implementing conversion of a DMA bus protocol; and
a high-speed clock domain, wherein
the high-speed clock domain comprises:
a software interaction interface, configured to control a central processing unit (CPU) to read/write a controller and a status register;
an interface clock generation unit, configured to generate an SPI clock signal after frequency division;
a data readback calibration unit, configured to receive data transmitted from an SPI flash;
a receiving control unit and a sending control unit, configured for receiving and sending data signals of the SPI flash; and
a pin delay control unit, configured to implement timing control of high-speed input/output (IO) of an SPI, wherein
the PLL provides two main clock signals by different clock frequency dividers, provides a low-speed clock signal to the low-speed clock domain, and provides a high-speed source clock signal to the high-speed clock domain.
2. The controller in a high-speed SPI master mode according to claim 1 , wherein the interface clock generation unit provides a clock signal to the pin delay control unit, the pin delay control unit is connected to the data readback calibration unit and provides a compensation clock to the data readback calibration unit, and the data readback calibration unit is connected to the receiving control unit.
3. The controller in a high-speed SPI master mode according to claim 2 , wherein a frequency of the high-speed source clock signal is fixed to an integer multiple of a frequency of the SPI clock signal.
4. The controller in a high-speed SPI master mode according to claim 3 , wherein the frequency of the high-speed source clock signal is fixed to 2 times the frequency of the SPI clock signal, and in this case, the interface clock generation unit generates an SPI clock after divide-by-2 frequency division.
5. The controller in a high-speed SPI master mode according to claim 1 , wherein a frequency of the high-speed source clock signal is fixed to an integer multiple of a frequency of the SPI clock signal.
6. The controller in a high-speed SPI master mode according to claim 5 , wherein the frequency of the high-speed source clock signal is fixed to 2 times the frequency of the SPI clock signal, and in this case, the interface clock generation unit generates an SPI clock after divide-by-2 frequency division.
7. The controller in a high-speed SPI master mode according to claim 1 , wherein the low-speed clock domain and the high-speed clock domain are isolated by data buffer units, and the data buffer units configured to perform isolation are a data receiving buffer unit and a data sending buffer unit.
8. The controller in a high-speed SPI master mode according to claim 7 , wherein both the data receiving buffer unit and the data sending buffer unit are asynchronous first in first out (FIFO) data buffer units.
9. The controller in a high-speed SPI master mode according to claim 1 , wherein the data readback calibration unit comprises two stages of registers connected to each other, an output terminal of a first stage register is connected to an input terminal of a second stage register, and an output terminal of the second stage register is connected to a shift register; and a clock signal of the first stage register comes from a compensation clock signal, and clock signals of the second stage register and the shift register both come from the high-speed source clock signal.
10. The controller in a high-speed SPI master mode according to claim 9 , wherein the second stage register latches output data of the first stage register by directly using a falling edge of the high-speed source clock signal, and an output of the second stage register is then latched to the shift register on a rising edge of the high-speed source clock signal through a combined logic path.
11. The controller in a high-speed SPI master mode according to claim 1 , wherein the pin delay control unit is provided with a compensation circuit configured to compensate for a delay of an SPI clock signal for sampling and receiving a data clock and a pin inside an SPI controller.
12. The controller in a high-speed SPI master mode according to claim 1 , wherein the software interaction interface supports selection of interface modes: a Dual SPI, a Quad SPI, or a standard SPI.