Flash memory scheme capable of decreasing waiting time of trim command

1. A flash memory controller used to be externally coupled to a host device and a flash memory, comprising:

a first Input/Output (I/O) interface circuit, coupled between the host device and a bus of the flash memory controller;

the bus;

a second I/O interface circuit, coupled to the bus and the flash memory; and

a multi-processor, having a plurality of processing units each being coupled to the bus, configured to:

receiving a trim command and a logical block address (LBA) range sent from the host device and transferred through the first I/O interface circuit and the bus;

separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range, N being an integer equal to or greater than two;

using the processing units to execute the N threads individually; and

increasing a number of execution cycles during which the processing units are busy;

wherein the N threads comprise at least one of following threads: a first thread of checking a state of the LBA range recorded in a logical-to-physical table stored in the flash memory, a second thread of allocating a direct memory access (DMA) first-in-first-out (FIFO) buffer, a third thread of allocating the flash memory's FIFO buffer, a fourth thread of performing a DMA service which is used for loading data of the LBA range and corresponding VPC data from the flash memory into the DMA FIFO buffer, a fifth thread of performing a memory service which is used for loading the data of the LBA range and the corresponding VPC data from the flash memory into the flash memory's FIFO buffer, and a sixth thread of executing a trim operation to erase the data of LBA range and update the corresponding VPC data by decrementing the corresponding VPC data by one sequentially.

2. The flash memory controller of claim 1 , wherein a number of the processing units is equal to a value of the N, and the multi-processor is arranged for respectively assigning one thread into each of processing units.

3. The flash memory controller of claim 1 , wherein a number of the processing units is smaller than a value of the N.

4. The flash memory controller of claim 1 , wherein the multi-processor divides a thread into multiple sub-threads which are executed by different processing units during a same execution cycle.

5. The flash memory controller of claim 4 , wherein the divided thread is the fourth thread, the fifth thread, or the sixth thread.

6. The flash memory controller of claim 1 , wherein the multi-processor divides a thread into multiple sub-threads which are executed by a single one processing unit during different execution cycles.

7. The flash memory controller of claim 6 , wherein the divided thread is the fourth thread, the fifth thread, or the sixth thread.

8. The flash memory controller of claim 1 , wherein the multi-core processor merges multiple threads into a larger thread which is executed by a single one processing unit during a continuous execution cycles.

9. The flash memory controller of claim 8 , wherein the merged threads are a group of the first thread, the second thread, and the third thread, a group of the fourth thread and the sixth thread, or a group of the fifth thread and the sixth thread.

10. The flash memory controller of claim 1 , wherein the flash memory controller is coupled to the flash memory through a plurality of channels, and the multi-core processor merges multiple threads for each channel into a larger thread which is executed by a single one processing unit during a continuous execution cycles; the merged threads are a group of the fifth thread and the sixth thread.

11. A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising:

providing a first Input/Output (I/O) interface circuit coupled between the host device and a bus of the flash memory controller;

providing a second I/O interface circuit coupled to a bus and the flash memory;

providing a multi-processor having a plurality of processing units each being coupled to the bus;

receiving a trim command and a logical block address (LBA) range sent from the host device and transferred through the first I/O interface circuit and the bus;

separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range, N being an integer equal to or greater than two;

using the processing units to execute the N threads individually; and

increasing a number of execution cycles during which the processing units are busy;

wherein the N threads comprise at least one of following threads: a first thread of checking a state of the LBA range recorded in a logical-to-physical table stored in the flash memory, a second thread of allocating a direct memory access (DMA) first-in-first-out (FIFO) buffer, a third thread of allocating the flash memory's FIFO buffer, a fourth thread of performing a DMA service which is used for loading data of the LBA range and corresponding VPC data from the flash memory into the DMA FIFO buffer, a fifth thread of performing a memory service which is used for loading the data of the LBA range and the corresponding VPC data from the flash memory into the flash memory's FIFO buffer, and a sixth thread of executing a trim operation to erase the data of LBA range and update the corresponding VPC data by decrementing the corresponding VPC data by one sequentially.

12. The method of claim 11 , wherein a number of the processing units is equal to a value of the N, and the method further comprises:

respectively assigning one thread into each of processing units.

13. The method of claim 11 , wherein a number of the processing units is smaller than a value of the N.

14. The method of claim 11 , further comprising:

dividing a thread into multiple sub-threads which are executed by different processing units during a same execution cycle.

15. The method of claim 14 , wherein the divided thread is the fourth thread, the fifth thread, or the sixth thread.

16. The method of claim 11 , further comprising:

dividing a thread into multiple sub-threads which are executed by a single one processing unit during different execution cycles.

17. The method of claim 16 , wherein the divided thread is the fourth thread, the fifth thread, or the sixth thread.

18. The method of claim 11 , further comprising:

merging multiple threads into a larger thread which is executed by a single one processing unit during a continuous execution cycles.

19. The method of claim 18 , wherein the merged threads are a group of the first thread, the second thread, and the third thread, a group of the fourth thread and the sixth thread, or a group of the fifth thread and the sixth thread.

20. The method of claim 11 , wherein the flash memory controller is coupled to the flash memory through a plurality of channels, and the method further comprises:

merging multiple threads for each channel into a larger thread which is executed by a single one processing unit during a continuous execution cycles; the merged threads are a group of the fifth thread and the sixth thread.