IP Library › Granted Patent US 11,810,494
Granted Patent B2
US 11,810,494 · App. 17/820,190 · Granted Nov 7, 2023

Dither enhancement of display gamma DAC systems and methods

Inventors: Jie Won Ryu (Santa Clara, CA); ByoungSuk Kim (Palo Alto, CA); David S Zalatimo (San Jose, CA); Graeme M Williams (San Diego, CA); Hyunsoo Kim (San Diego, CA); Hyunwoo Nho (Palo Alto, CA); Jesse R Manders (San Francisco, CA); Kingsuk Brahma (Mountain View, CA); Li-Xuan Chuo (San Jose, CA); Sachiko Oda (Santa Clara, CA); Shatam Agarwal (San Jose, CA); Yao Shi (Sunnyvale, CA)
Assignee: Apple Inc.
G09G3/2044H03M1/1019G09G2310/027G09G2320/0276
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Quick Facts
Patent No.
US 11,810,494
App. No.
17/820,190
Granted
Nov 7, 2023
Kind
B2
Abstract

An electronic device may include an electronic display having multiple display pixels to display an image based on analog voltage signals. The electronic device may also include optical calibration circuitry to generate digital-to-analog converter (DAC) data based on image data associated with the image and dither circuitry to reduce a bit-depth of the DAC data, generating dithered DAC data. Additionally, the electronic device may include a gamma generator having one or more DACs to generate the analog voltage signals based on the dithered DAC data, which may instruct the gamma generator to generate the analog voltage signals indicative of the image data.

Claims (36)

1. An electronic device comprising:

an electronic display comprising a plurality of display pixels configured to display an image based at least in part on a plurality of analog voltage signals;

optical calibration circuitry configured to generate digital-to-analog converter (DAC) data based at least in part on image data associated with the image;

dither circuitry configured to reduce a bit-depth of the DAC data, generating dithered DAC data; and

a gamma generator comprising one or more DACs configured to generate the analog voltage signals based at least in part on the dithered DAC data, wherein the dithered DAC data is configured to instruct the gamma generator to generate the plurality of analog voltage signals indicative of the image data, wherein the gamma generator is physically separated from the dither circuitry by a data bus, and wherein the data bus is configured to transmit the dithered DAC data to the gamma generator at the reduced bit-depth.

2. The electronic device of claim 1 , wherein the optical calibration circuitry is configured to generate the DAC data by transforming the image data from a gray code domain to a DAC code domain, wherein the gamma generator is configured to operate in the DAC code domain.

3. The electronic device of claim 1 , wherein the image data comprises processed image data, the electronic device comprising image processing circuitry configured to generate the processed image data based at least in part on input image data.

4. The electronic device of claim 3 , wherein the image processing circuitry comprises a dither block configured to dither the input image data.

5. The electronic device of claim 3 , wherein the image processing circuitry is configured to process the input image data and generate the processed image data in a gray code domain, wherein the gamma generator is configured to operate in a DAC code domain.

6. The electronic device of claim 1 , wherein the dither circuitry is configured to spatially dither or spatiotemporally dither the DAC data.

7. The electronic device of claim 1 , wherein the optical calibration circuitry comprises a look-up table (LUT) configured to map the image data to the DAC data.

8. The electronic device of claim 1 , wherein the dither circuitry is configured to reduce the bit-depth of the DAC data directly prior to the gamma generator.

9. The electronic device of claim 1 , wherein generating the DAC data based at least in part on the image data comprises mapping the image data from a gray code domain to a DAC code domain and increasing a bit-depth of the image data to the bit-depth of the DAC data.

10. A method comprising:

processing, via image processing circuitry, input image data in a gray code domain to generate processed image data;

transforming, via optical calibration circuitry, the processed image data in the gray code domain to a digital-to-analog converter (DAC) code domain to generate DAC data, wherein transforming the processed image data comprises upscaling the processed image data, increasing a bit-depth of the processed image data;

dithering, via dither circuitry, the DAC data in the DAC code domain to generate dithered DAC data;

converting, via a DAC, the dithered DAC data in the DAC code domain to an analog voltage in an analog domain; and

outputting, the analog voltage to an electronic display in the analog domain.

11. The method of claim 10 , wherein dithering the DAC data comprises temporally dithering or spatiotemporally dithering the DAC data.

12. The method of claim 10 , wherein the image processing circuitry comprises second dither circuitry configured to dither the input image data in the gray code domain.

13. The method of claim 10 , wherein transforming the processed image data comprises mapping the processed image data from the gray code domain to the DAC code domain via a look-up table (LUT).

14. The method of claim 13 , wherein the LUT is configured to upscale the processed image data.

15. The method of claim 10 , comprising selecting a dither mode of the dither circuitry based at least in part on an operating mode of the electronic display.

16. An electronic display comprising:

a plurality of pixels;

one or more display drivers configured to drive analog voltages to the plurality of pixels;

a gamma generator configured to generate the analog voltages based at least in part on dithered digital-to-analog converter (DAC) data in a DAC code format; and

circuitry configured to:

transform image data from a gray code format to the DAC code format, generating DAC data, based at least in part on an optical calibration mapping;

dither the DAC data in the DAC code format to generate dithered DAC data at a reduced bit-depth in the DAC code format; and

output the dithered DAC data in the DAC code format to the gamma generator, wherein the gamma generator is physically separated from the circuitry by a data bus, wherein the data bus is configured to transmit the dithered DAC data to the gamma generator at the reduced bit-depth.

17. The electronic display of claim 16 , wherein the DAC code format of the DAC data or the dithered DAC data is associated with a type of the gamma generator.

18. The electronic display of claim 16 , wherein the optical calibration mapping comprises a mapping algorithm.

19. The electronic display of claim 16 , wherein the circuitry is configured to receive the image data in the gray code format from image processing circuitry.

20. The electronic display of claim 16 , wherein the dithered DAC data is not altered between dithering and outputting of the dithered DAC data to the gamma generator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2022
From: RYU, JIE WON; NHO, HYUNWOO; KIM, HYUNSOO; AGARWAL, SHATAM; WILLIAMS, GRAEME M; BRAHMA, KINGSUK; MANDERS, JESSE R; SHI, YAO; ODA, SACHIKO; ZALATIMO, DAVID S; KIM, BYOUNGSUK; CHUO, LI-XUAN
To: APPLE INC.
Reel/Frame 061078/0758 →
Continuity (2)
Provisional Application 63247165 · Sep 22, 2021
Related Publication 20230087480A1 · Mar 23, 2023