Integrated circuit device including capacitor with metal nitrate interfacial layer
A capacitor includes: a lower electrode including a metal nitride represented by MM′N, wherein M is a metal element, M′ is an element different from M, and N is nitrogen; a dielectric layer on the lower electrode; an interfacial layer between the lower electrode and the dielectric layer and including a metal nitrate represented by MM′ON, wherein M is a metal element, M′ is an element different from M, N is nitrogen, and O is oxygen; and an upper electrode on the dielectric layer.
1. An integrated circuit device, comprising:
a substrate; and
a capacitor on the substrate,
wherein the capacitor comprises
a lower electrode including a metal nitride,
a dielectric layer on the lower electrode, the dielectric layer including a metal oxide including at least one of Hf, Zr, Al, Nb, Ce, La, Ta, and Ti,
an interfacial layer between the lower electrode and the dielectric layer, the interfacial layer including M, M′, N and O, wherein M is Ti and M′ is Nb, and
an upper electrode on the dielectric layer, the upper electrode including Ti and N.
2. The integrated circuit device of claim 1 , wherein the dielectric layer includes a multi-layer structure, and at least one layer of the multi-layer structure includes the metal oxide including at least one of Hf, Zr, Al, Nb, Ce, La, Ta, and Ti.
3. The integrated circuit device of claim 1 , wherein the lower electrode includes Ti and N.
4. The integrated circuit device of claim 3 , wherein the lower electrode further includes Nb.
5. The integrated circuit device of claim 1 , wherein the interfacial layer is in direct contact with the lower electrode.
6. The integrated circuit device of claim 1 , wherein a content of carbon impurities in the lower electrode is 1% or less.
7. The integrated circuit device of claim 1 , wherein, in the capacitor, a change range of capacitance C with respect to a bias voltage is represented by C min ≤C≤C max , and C min /C max is 0.9 or more.
8. The integrated circuit device of claim 1 , wherein the substrate includes:
a semiconductor substrate;
at least one conductive region on the semiconductor substrate; and
an insulating film insulating the at least one conductive region.
9. An electronic device, comprising:
a transistor; and
a capacitor connected to the transistor,
wherein the capacitor comprises
a lower electrode including a metal nitride,
a dielectric layer on the lower electrode, the dielectric layer including a metal oxide including at least one of Hf, Zr, Al, Nb, Ce, La, Ta, and Ti,
an interfacial layer between the lower electrode and the dielectric layer, the interfacial layer including M, M′, N and O, wherein M is Ti and M′ is Nb, and
an upper electrode on the dielectric layer, the upper electrode including Ti and N.
10. The electronic device of claim 9 , wherein the dielectric layer includes a multi-layer structure, and at least one layer of the multi-layer structure includes the metal oxide including at least one of Hf, Zr, Al, Nb, Ce, La, Ta, and Ti.
11. The electronic device of claim 9 , wherein the lower electrode includes Ti and N.
12. The electronic device of claim 11 , wherein the lower electrode further includes Nb.
13. The electronic device of claim 9 , wherein the interfacial layer is in direct contact with the lower electrode.
14. The electronic device of claim 9 , wherein, in the capacitor, a change range of capacitance C with respect to a bias voltage is represented by C min ≤C≤C max , and C min /C max is 0.9 or more.
15. An electronic device, comprising:
a memory device including a plurality of memory cells; and
a controller configured to read data from the memory device or to write data into the memory device,
wherein each of the plurality of memory cells includes a transistor and a capacitor connected to the transistor,
wherein the capacitor comprises
a lower electrode including a metal nitride,
a dielectric layer on the lower electrode, the dielectric layer including a metal oxide including at least one of Hf, Zr, Al, Nb, Ce, La, Ta, and Ti,
an interfacial layer between the lower electrode and the dielectric layer, the interfacial layer including M, M′, N and O, wherein M is Ti and M′ is Nb, and
an upper electrode on the dielectric layer, the upper electrode including Ti and N.
16. The electronic device of claim 15 , wherein the dielectric layer includes a multi-layer structure, and at least one layer of the multi-layer structure includes the metal oxide including at least one of Hf, Zr, Al, Nb, Ce, La, Ta, and Ti.
17. The electronic device of claim 15 , wherein the lower electrode includes Ti and N.
18. The electronic device of claim 17 , wherein the lower electrode further includes Nb.
19. The electronic device of claim 15 , wherein the interfacial layer is in direct contact with the lower electrode.
20. The electronic device of claim 15 , wherein, in the capacitor, a change range of capacitance C with respect to a bias voltage is represented by C min ≤C≤C max , and C min /C max is 0.9 or more.