Faceplate having blocked center hole
Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a central recess about the central axis extending from the second surface of the faceplate to a depth less than a thickness of the faceplate.
1. A semiconductor processing chamber comprising:
a gasbox;
a substrate support;
a blocker plate positioned between the gasbox and the substrate support, wherein the blocker plate defines a plurality of blocker plate apertures through the blocker plate; and
a faceplate positioned between the blocker plate and the substrate support, wherein the faceplate is characterized by a first surface facing the blocker plate and a second surface opposite the first surface, wherein the second surface of the faceplate and the substrate support at least partially define a processing region within the semiconductor processing chamber, wherein the faceplate is characterized by a central axis, wherein the faceplate defines a plurality of faceplate apertures through the faceplate, wherein the faceplate defines a central recess about the central axis extending from the second surface of the faceplate to a depth less than a thickness of the faceplate, and
wherein the central recess defines a blind hole, and
wherein each faceplate aperture comprises an aperture profile characterized by a first section extending from the first surface to a position partially through the faceplate, and further characterized by a second section extending from the position partially through the faceplate to the second surface, wherein the central recess is characterized by a substantially identical profile as the second section of the aperture profile of each faceplate aperture.
2. The semiconductor processing chamber of claim 1 , wherein the faceplate is substantially planar across the first surface about the central axis.
3. The semiconductor processing chamber of claim 1 , further comprising an electrical source configured to strike a plasma within the processing region of the semiconductor processing chamber.
4. The semiconductor processing chamber of claim 1 , wherein the first section is characterized by a substantially cylindrical profile.
5. The semiconductor processing chamber of claim 1 , wherein the second section comprises a conical or countersunk profile.
6. The semiconductor processing chamber of claim 1 , wherein the central recess extends less than halfway through the thickness of the faceplate from the second surface.
7. A semiconductor processing chamber faceplate, comprising:
a first surface and a second surface opposite the first surface, wherein:
the faceplate is characterized by a central axis extending through the first surface and the second surface,
the faceplate defines a plurality of faceplate apertures through the faceplate, and
the faceplate defines a central recess along the central axis and extending from the second surface of the faceplate to a depth less than a thickness of the faceplate; and
wherein the central recess defines a blind hole, and
wherein each faceplate aperture comprises an aperture profile characterized by a first section extending from the first surface to a position partially through the faceplate, and further characterized by a second section extending from the position partially through the faceplate to the second surface, wherein the central recess is characterized by a substantially identical profile as the second section of the aperture profile of each faceplate aperture.
8. The semiconductor processing chamber faceplate of claim 7 , wherein the faceplate is substantially planar across the first surface about the central axis.
9. The semiconductor processing chamber faceplate of claim 7 , wherein the aperture profile of each faceplate aperture includes a taper extending from the second surface.
10. The semiconductor processing chamber faceplate of claim 9 , wherein the taper extends to a depth partway through the thickness of the faceplate, and wherein the profile of each faceplate aperture transitions to a choke from the taper.
11. The semiconductor processing chamber faceplate of claim 10 , wherein the aperture profile of each faceplate aperture transitions from the choke to a substantially cylindrical profile extending to the first surface.
12. The semiconductor processing chamber faceplate of claim 10 , wherein the profile of the central recess is identical to the taper of the aperture profile of each faceplate aperture.
13. The semiconductor processing chamber faceplate of claim 12 , wherein the profile of the central recess transitions to a substantially cylindrical profile extending to a location less than the thickness of the faceplate.
14. The semiconductor processing chamber faceplate of claim 7 , wherein the central recess extends less than halfway through the thickness of the faceplate from the second surface.
15. A method of semiconductor processing comprising:
flowing a precursor into a processing chamber, wherein the processing chamber comprises a faceplate and a substrate support on which a substrate is disposed, wherein a processing region of the processing chamber is at least partially defined between the faceplate and the substrate support,
wherein the faceplate defines:
a first surface and a second surface opposite the first surface, wherein:
the faceplate is characterized by a central axis extending through the first surface and the second surface,
the faceplate defines a plurality of faceplate apertures through the faceplate, and
the faceplate defines a central recess along the central axis and extending from the second surface of the faceplate to a depth less than a thickness of the faceplate, and
wherein the central recess defines a blind hole; and
wherein each faceplate aperture comprises an aperture profile characterized by a first section extending from the first surface to a position partially through the faceplate, and further characterized by a second section extending from the position partially through the faceplate to the second surface, wherein the central recess is characterized by a substantially identical profile as the second section of the aperture profile of each faceplate aperture;
generating a plasma of the precursor within the processing region of the processing chamber;
depositing a material on the substrate.
16. The method of semiconductor processing of claim 15 , wherein the material deposited is characterized by thickness at a center portion of the substrate less than 10% greater than a thickness at an edge portion of the substrate.
17. The method of semiconductor processing of claim 15 , wherein the central recess is characterized by a conical or countersunk profile.