Enabling secure communication via attestation of multi-tenant configuration on accelerator devices

1. An apparatus comprising:

a processor to:

verify a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP);

verify partial reconfiguration (PR) boundary setups and PR isolation of an accelerator device, the PR boundary setups and PR isolation published by the CSP;

generate PR bitstream to fit within at least one PR region of the PR boundary setups of the accelerator device;

inspect accelerator device attestation received from a secure device manager (SDM) of the accelerator device; and

responsive to successful inspection of the accelerator device attestation, provide the PR bitstream to the CSP for PR reconfiguration of the accelerator device.

2. The apparatus of claim 1 , wherein the SDM comprises a configuration manager and security enclave for the accelerator device.

3. The apparatus of claim 1 , wherein a circuit design tool is utilized to inspect and verify the base bitstream, the PR boundary setups, and the PR isolation.

4. The apparatus of claim 3 , wherein the circuit design tool is utilized to generate the PR bitstream.

5. The apparatus of claim 1 , wherein a trusted agent of the CSP provides the accelerator device attestation.

6. The apparatus of claim 5 , wherein the SDM provides the accelerator device attestation to the trusted agent.

7. The apparatus of claim 1 , wherein the accelerator device attestation comprises an immutable accelerator device identifier (ID), a base bitstream ID, and a hash of a PR mask.

8. The apparatus of claim 1 , wherein the accelerator device comprises at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC).

9. The apparatus of claim 8 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

10. A method comprising:

verifying, by one or more processors, a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP);

verifying partial reconfiguration (PR) boundary setups and PR isolation of an accelerator device, the PR boundary setups and PR isolation published by the CSP;

generating PR bitstream to fit within at least one PR region of the PR boundary setups of the accelerator device;

inspecting accelerator device attestation received from a secure device manager (SDM) of the accelerator device; and

responsive to successful inspection of the accelerator device attestation, providing the PR bitstream to the CSP for PR reconfiguration of the accelerator device.

11. The method of claim 10 , wherein a circuit design tool is utilized to inspect and verify the base bitstream, the PR boundary setups, and the PR isolation.

12. The method of claim 11 , wherein the circuit design tool is utilized to generate the PR bitstream.

13. The method of claim 10 , wherein a trusted agent of the CSP provides the accelerator device attestation, and wherein the SDM provides the accelerator device attestation to the trusted agent.

14. The method of claim 10 , wherein the accelerator device attestation comprises an immutable accelerator device identifier (ID), a base bitstream ID, and a hash of a PR mask.

15. The method of claim 10 , wherein the accelerator device comprises at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC), and wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

16. A non-transitory machine readable storage medium comprising instructions that, when executed, cause at least one processor to at least:

verify, by the at least one processor, a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP);

verify partial reconfiguration (PR) boundary setups and PR isolation of an accelerator device, the PR boundary setups and PR isolation published by the CSP;

generate PR bitstream to fit within at least one PR region of the PR boundary setups of the accelerator device;

inspect accelerator device attestation received from a secure device manager (SDM) of the accelerator device; and

responsive to successful inspection of the accelerator device attestation, provide the PR bitstream to the CSP for PR reconfiguration of the accelerator device.

17. The non-transitory machine readable storage medium of claim 16 , wherein a circuit design tool is utilized to inspect and verify the base bitstream, the PR boundary setups, and the PR isolation.

18. The non-transitory machine readable storage medium of claim 17 , wherein the circuit design tool is utilized to generate the PR bitstream.

19. The non-transitory machine readable storage medium of claim 16 , wherein a trusted agent of the CSP provides the accelerator device attestation, and wherein the SDM provides the accelerator device attestation to the trusted agent.

20. The non-transitory machine readable storage medium of claim 16 , wherein the accelerator device attestation comprises an immutable accelerator device identifier (ID), a base bitstream ID, and a hash of a PR mask.