Circuit for detecting anti-fuse memory cell state and memory
A circuit for detecting an anti-fuse memory cell state includes a current providing module connected to a first node and used to provide constant current; an anti-fuse memory cell array connected to the first node and including at least one bit line, the at least one bit line is connected to a plurality of anti-fuse memory cells and the first node; and a comparator, a first input end of the comparator is connected to the first node and a second input end of the comparator is connected to a first reference voltage, and used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array.
1. A circuit for detecting an anti-fuse memory cell state, comprising:
a current providing module connected to a first node and used to provide constant current;
an anti-fuse memory cell array connected to the first node and comprising at least one bit line, the at least one bit line being connected to a plurality of anti-fuse memory cells and the first node; and
a comparator, wherein a first input end of the comparator is connected to the first node, a second input end of the comparator is connected to a first reference voltage, and the comparator is used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array;
wherein the current providing module comprises:
an amplifier, wherein a first input end of the amplifier is connected to a second reference voltage, a second input end of the amplifier is connected to a second node, and an output end of the amplifier is connected to a third node;
a first switching element, wherein a first end of the first switching element is connected to a power voltage, a second end of the first switching element is connected to the second node, and a control end of the first switching element is connected to the third node;
a reference resistor, wherein a first end of the reference resistor is connected to the second node and a second end of the reference resistor is grounded; and
a second switching element, wherein a first end of the second switching element is connected to the power voltage, a second end of the second switching element is connected to the first node and a control end of the second switching element is connected to the third node.
2. The circuit for detecting the anti-fuse memory cell state of claim 1 , further comprising:
a flip-flop, an input end of the flip-flop being connected to an output end of the comparator.
3. The circuit for detecting the anti-fuse memory cell state of claim 1 , wherein word lines of the plurality of anti-fuse memory cells and the output end of the comparator are connected with a controller.
4. The circuit for detecting the anti-fuse memory cell state of claim 2 , wherein word lines of the plurality of anti-fuse memory cells and an output end of the flip-flop are connected with a controller.
5. The circuit for detecting the anti-fuse memory cell state of claim 3 , wherein the controller is configured to:
control the anti-fuse memory cell to be tested to be electrically connected to a respective bit line by outputting a first control signal at a first time point to a word line of the anti-fuse memory cell to be tested, and
determine a storage state of the anti-fuse memory cell to be tested by acquiring an output signal of the comparator at a second time point;
wherein the second time point is later than the first time point.
6. The circuit for detecting the anti-fuse memory cell state of claim 4 , wherein the controller is configured to:
control the anti-fuse memory cell to be tested to be electrically connected to a respective bit line by outputting a first control signal at a first time point to a word line of the anti-fuse memory cell to be tested, and
determine a storage state of the anti-fuse memory cell to be tested by acquiring an output signal of the comparator at a second time point;
wherein the second time point is later than the first time point.
7. The circuit for detecting the anti-fuse memory cell state of claim 1 , wherein the reference resistor is a ZQ calibration resistor.
8. The circuit for detecting the anti-fuse memory cell state of claim 7 , wherein a first end of the reference resistor is connected to the second node through a third switching element; a control end of the third switching element is connected to a controller; the controller is configured to control the third switching element to be switched on at a third time point; and the third time point is earlier than the second time point.
9. The circuit for detecting the anti-fuse memory cell state of claim 1 , wherein the anti-fuse memory cell array comprises:
a plurality of anti-fuse memory cell sub-arrays, each anti-fuse memory cell sub-array corresponding to one bit line, and each anti-fuse memory cell sub-array comprising a plurality of anti-fuse memory cells; and
a plurality of switching elements corresponding to the anti-fuse memory cell sub-arrays, a first end of each switching element being connected to a bit line of the corresponding anti-fuse memory cell sub-array and a second end of each switching element being connected to the first node, wherein a default state of the switching element is an off state.
10. The circuit for detecting the anti-fuse memory cell state of claim 9 , wherein a control end of each switching element is connected to a controller, and the controller is configured to:
control a switching element to be switched on by outputting a second control signal at a fourth time point to the switching element corresponding to an anti-fuse memory cell sub-array in which the anti-fuse memory cell to be tested is located;
control the anti-fuse memory cell to be tested to be electrically connected to a respective bit line by outputting a first control signal at a first time point to a word line of the anti-fuse memory cell to be tested to; and
determine a storage state of the anti-fuse memory cell to be tested by acquiring an output signal of the comparator at a second time point,
wherein the fourth time point is earlier than the second time point.
11. A memory, comprising circuit for detecting the anti-fuse memory cell state, wherein the circuit for detecting the anti-fuse memory cell state comprises:
a current providing module connected to a first node and used to provide constant current;
an anti-fuse memory cell array connected to the first node and comprising at least one bit line, the at least one bit line being connected to a plurality of anti-fuse memory cells and the first node; and
a comparator, wherein a first input end of the comparator is connected to the first node, a second input end of the comparator is connected to a first reference voltage, and the comparator is used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array;
wherein the current providing module comprises:
an amplifier, wherein a first input end of the amplifier is connected to a second reference voltage, a second input end of the amplifier is connected to a second node, and an output end of the amplifier is connected to a third node;
a first switching element, wherein a first end of the first switching element is connected to a power voltage, a second end of the first switching element is connected to the second node, and a control end of the first switching element is connected to the third node;
a reference resistor, wherein a first end of the reference resistor is connected to the second node and a second end of the reference resistor is grounded; and
a second switching element, wherein a first end of the second switching element is connected to the power voltage, a second end of the second switching element is connected to the first node and a control end of the second switching element is connected to the third node.
12. The memory of claim 11 , wherein the circuit for detecting the anti-fuse memory cell state further comprises:
a flip-flop, an input end of the flip-flop being connected to an output end of the comparator.
13. The memory of claim 11 , wherein word lines of the plurality of anti-fuse memory cells and the output end of the comparator are connected with a controller.
14. The memory of claim 12 , wherein word lines of the plurality of anti-fuse memory cells and an output end of the flip-flop are connected with a controller.
15. The memory of claim 13 , wherein the controller is configured to:
control the anti-fuse memory cell to be tested to be electrically connected to a respective bit line by outputting a first control signal at a first time point to a word line of the anti-fuse memory cell to be tested, and
determine a storage state of the anti-fuse memory cell to be tested by acquiring an output signal of the comparator at a second time point;
wherein the second time point is later than the first time point.
16. The memory of claim 14 , wherein the controller is configured to:
control the anti-fuse memory cell to be tested to be electrically connected to a respective bit line by outputting a first control signal at a first time point to a word line of the anti-fuse memory cell to be tested, and
determine a storage state of the anti-fuse memory cell to be tested by acquiring an output signal of the comparator at a second time point;
wherein the second time point is later than the first time point.