IP Library › Granted Patent US 11,818,844
Granted Patent B2
US 11,818,844 · App. 17/826,013 · Granted Nov 14, 2023

Semiconductor module and electronic apparatus

Inventors: Yuya Karakawa (Kanagawa, JP); Mitsutoshi Hasegawa (Kanagawa, JP); Takashi Aoki (Chiba, JP); Noritake Tsuboi (Kanagawa, JP)
Assignee: Canon Kabushiki Kaisha
H05K1/181H01L23/49816H05K3/3452H05K3/3485H05K1/148H05K2201/0989H05K2201/10015H05K2201/1053H05K2201/10378H05K2201/10515H05K2201/10636H05K2201/10734H05K2203/048H05K2203/306
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Quick Facts
Patent No.
US 11,818,844
App. No.
17/826,013
Granted
Nov 14, 2023
Kind
B2
Abstract

A semiconductor module includes a semiconductor device having a first land, a second land, and a third land, a wiring board having a substrate, and a fourth land, a fifth land, and a sixth land disposed on the main surface of the substrate, a chip component having a first electrode and a second electrode disposed across a distance in the longitudinal direction and being disposed between the wiring board and the semiconductor device, a first solder joint for bonding the first land, the fourth land, and the first electrode, a second solder joint for bonding the second land, the fifth land, and the second electrode, and a third solder joint for bonding the third land and the sixth land. The volume of the first solder joint and the volume of the second solder joint are each larger than the volume of the third solder joint.

Claims (44)

1. A semiconductor module comprising: a semiconductor device having a first land, a second land, and a third land; a wiring board having a substrate, a fourth land, a fifth land, and a sixth land disposed on a main surface of the substrate; a chip component having a first electrode and a second electrode disposed across a distance in a longitudinal direction and being disposed between the wiring board and the semiconductor device; a first solder joint configured to bond the first land, the fourth land, and the first electrode; a second solder joint configured to bond the second land, the fifth land, and the second electrode; and a third solder joint configured to bond the third land and the sixth land, wherein a volume of the first solder joint and a volume of the second solder joint are each larger than a volume of the third solder joint, wherein the volume of the first solder joint is greater than or equal to 1.2 times the volume of the third solder joint, and wherein the volume of the second solder joint is greater than or equal to 1.2 times the volume of the third solder joint.

2. The semiconductor module according to claim 1 , wherein an area of a largest land of the fourth land, the fifth land, and the sixth land is less than or equal to 1.1 times an area of a smallest land of the fourth land, the fifth land, and the sixth land.

3. The semiconductor module according to claim 1 ,

wherein the first electrode of the chip component is separated from the first land of the semiconductor device,

wherein the first electrode of the chip component is separated from the fourth land of the wiring board,

wherein the second electrode of the chip component is separated from the second land of the semiconductor device, and

wherein the second electrode of the chip component is separated from the fifth land of the wiring board.

4. The semiconductor module according to claim 1 ,

wherein the first solder joint and the third solder joint are adjacent to each other in a first direction, and

wherein a length of the first solder joint in the first direction is greater than a length of the third solder joint in the first direction.

5. The semiconductor module according to claim 1 ,

wherein the wiring board is a printed wiring board,

wherein the printed wiring board has a solder resist, the solder resist being disposed on the main surface of the substrate and having a plurality of openings and a plurality of guiding portions,

wherein the semiconductor module further includes a first conductor pattern, the first conductor pattern being disposed on the main surface of the substrate and extending from the fourth land in a first direction intersecting with the longitudinal direction of the chip component,

wherein the semiconductor module further includes a second conductor pattern, the second conductor pattern being disposed on the main surface of the substrate and extending from the fifth land in a second direction intersecting with the longitudinal direction of the chip component,

wherein the fourth land, the fifth land, and the sixth land are exposed from the plurality of openings, and

wherein the first conductor pattern and the second conductor pattern are each covered by one or more of the plurality of guiding portions of the solder resist.

6. The semiconductor module according to claim 1 , wherein the chip component is a chip component of a size smaller or equal to 0402 size.

7. The semiconductor module according to claim 1 , wherein the chip component is a capacitor.

8. The semiconductor module according to claim 1 , wherein the semiconductor device is a semiconductor package with a ball grid array (BGA) in which a distance between lands is less than or equal to 0.4 mm.

9. An electronic apparatus comprising:

a housing; and

the semiconductor module according to claim 1 disposed inside the housing.

10. A semiconductor module comprising: a semiconductor device having a first land and a second land; a printed wiring board having an insulating substrate, a solder resist having a plurality of openings and a plurality of guiding portions disposed on a main surface of the insulating substrate, and a fourth land and a fifth land exposed from the plurality of openings disposed on the main surface of the insulating substrate; a chip component having a first electrode and a second electrode disposed across a distance in a longitudinal direction and being disposed between the printed wiring board and the semiconductor device; a first solder joint configured to bond the first land, the fourth land, and the first electrode; a second solder joint configured to bond the second land, the fifth land, and the second electrode; a first conductor pattern extending from the fourth land disposed on the main surface of the insulating substrate in a first direction intersecting with the longitudinal direction of the chip component; and a second conductor pattern extending from the fifth land disposed on the main surface of the insulating substrate in a second direction intersecting with the longitudinal direction of the chip component, wherein the first conductor pattern and the second conductor pattern are each covered by one or more of the plurality of guiding portions of the solder resist, wherein a width of the first conductor pattern is larger than or equal to a length of the first electrode in the longitudinal direction of the chip component, and wherein a width of the second conductor pattern is larger than or equal to a length of the second electrode in the longitudinal direction of the chip component.

11. The semiconductor module according to claim 10 ,

wherein the printed wiring board further includes a plurality of sixth lands on the main surface of the insulating substrate, the plurality of sixth lands being disposed more in a vicinity of an outer edge of the main surface of the insulating substrate than the fourth land,

wherein a length of the first conductor pattern in the first direction is larger than a half of a widthwise length of the chip component, and is shorter than a shortest distance between the fourth land and the plurality of sixth lands, and

wherein a length of the second conductor pattern in the second direction is larger than a half of the widthwise length of the chip component, and is shorter than a shortest distance between the fifth land and the plurality of sixth lands.

12. The semiconductor module according to claim 11 ,

wherein the semiconductor device further comprises a third land, the third land being adjacent to the first land and/or the second land,

wherein the semiconductor module further comprises a third solder joint configured to bond the third land and the sixth land, and

wherein a volume of the first solder joint and a volume of the second solder joint are each larger than a volume of the third solder joint.

13. The semiconductor module according to claim 10 ,

wherein the first land and the second land are each disposed on an outermost periphery,

wherein a length of the first conductor pattern in the first direction is larger than a half of a widthwise length of the chip component,

wherein a length of the second conductor pattern in the second direction is larger than a half of the widthwise length of the chip component, and

wherein, when the semiconductor module is viewed from a top surface, the first conductor pattern and the second conductor pattern extend to outside of the semiconductor device.

14. The semiconductor module according to claim 10 , wherein flux is disposed on the at least one of the plurality of guiding portions of the solder resist.

15. The semiconductor module according to claim 14 , wherein the flux is disposed only on the plurality of guiding portions on the solder resist.

16. The semiconductor module according to claim 10 , wherein the first conductor pattern and the second conductor pattern are not connected with wiring.

17. The semiconductor module according to claim 10 , wherein the first conductor pattern extends from the third land in a direction approaching the second conductor pattern.

18. An electronic apparatus comprising:

a housing; and

the semiconductor module according to claim 10 disposed inside the housing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2023
From: KARAKAWA, YUYA; HASEGAWA, MITSUTOSHI; AOKI, TAKASHI; TSUBOI, NORITAKE
To: CANON KABUSHIKI KAISHA
Reel/Frame 065112/0362 →
Priority Claims (2)
JP 2021-091341 · May 31, 2021 · national
JP 2021-091342 · May 31, 2021 · national
Continuity (1)
Related Publication 20220386468A1 · Dec 1, 2022