Semiconductor device including ferroelectric layer and metal particles embedded in metal-organic framework layer

1. A semiconductor device comprising;

a substrate;

a ferroelectric layer disposed on the substrate;

a charge trap layer disposed on the ferroelectric layer;

a gate insulation layer disposed on the charge trap layer; and

a gate electrode layer disposed on the gate insulation layer,

wherein the charge trap layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

2. The semiconductor device of claim 1 , further comprising a source region and a drain region respectively disposed in different regions of the substrate.

3. The semiconductor device of claim 1 , wherein the ferroelectric layer includes at least one selected from hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

4. The semiconductor device of claim 1 , wherein the metal-organic framework layer includes a two-dimensional conductive metal-organic framework that includes cavities.

5. The semiconductor device of claim 4 ,

wherein the metal-organic framework layer includes at least two conductive metal-organic frameworks stacked on the ferroelectric layer,

wherein the cavities of the at least two conductive metal-organic frameworks are disposed to overlap with each other in a thickness direction of the metal-organic framework layer, and

wherein the metal particles are disposed inside the overlapping cavities.

6. The semiconductor device of claim 4 , wherein the conductive metal-organic framework includes at least one selected from hexahydroxytriphenylene, hexaiminotriphenylene, hexathioltriphenylene, hexahydrobenzene, hexaaminobenzene, and hexathiolbenzene.

7. The semiconductor device of claim 1 , wherein the metal particle includes at least one selected from cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and manganese (Mg).

8. The semiconductor device of claim 1 , wherein the metal particles are configured to trap or de-trap electric charges depending on a polarity of a voltage applied between the gate electrode layer and the substrate.

9. The semiconductor device of claim 1 , wherein the metal particles are regularly arranged in the metal-organic framework layer.

10. A semiconductor device comprising:

a substrate;

a channel layer disposed over the substrate in a vertical direction;

a ferroelectric layer disposed on the channel layer;

a charge trap layer disposed on the ferroelectric layer;

a gate insulation layer disposed on the charge trap layer;

a gate electrode layer disposed on the gate insulation layer; and

a source electrode layer and a drain electrode layer disposed to respectively contact opposite ends of the channel layer over the substrate,

wherein the charge trap layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

11. The semiconductor device of claim 10 , wherein the channel layer includes a semiconductor material.

12. The semiconductor device of claim 10 , wherein the metal-organic framework layer includes two-dimensional conductive metal-organic frameworks that include cavities.

13. The semiconductor device of claim 12 ,

wherein the metal-organic framework layer includes at least two conductive metal-organic frameworks stacked on the ferroelectric layer,

wherein the cavities of the at least two conductive metal-organic frameworks are disposed to overlap with each other in a thickness direction of the metal-organic framework layer, and

wherein the metal particles are disposed in interior spaces of the overlapping cavities.

14. A semiconductor device comprising:

a substrate;

a gate structure including a hole pattern over the substrate, the gate structure including gate electrode layers and interlayer insulation layers, which are alternately stacked over the substrate;

a gate insulation layer disposed on a sidewall surface of the gate structure exposed by the hole pattern;

a charge trap layer disposed on the gate insulation layer;

a ferroelectric layer disposed on the charge trap layer; and

a channel layer disposed on the ferroelectric layer,

wherein the charge trap layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.

15. The semiconductor device of claim 14 , wherein the channel layer extends in a direction substantially perpendicular to a surface of the substrate.

16. The semiconductor device of claim 14 , further comprising a source line and a bit line electrically connected to opposite ends of the channel layer, respectively.

17. The semiconductor device of claim 14 , wherein the metal-organic framework layer includes two-dimensional conductive metal-organic frameworks that form cavities.

18. The semiconductor device of claim 17 ,

wherein the metal-organic framework layer includes at least two conductive metal-organic frameworks stacked over the gate insulation layer,

wherein the cavities of the at least two conductive metal-organic frameworks are disposed to overlap with each other in a thickness direction of the metal-organic framework layer, and

wherein the metal particles are disposed inside the overlapping cavities.

19. The semiconductor device of claim 14 , wherein the conductive metal-organic framework includes at least one selected from hexahydroxytriphenylene, hexaiminotriphenylene, hexathioltriphenylene, hexahydrobenzene, hexaaminobenzene, and hexathiolbenzene.

20. The semiconductor device of claim 14 , wherein the metal particle includes at least one selected from cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and manganese (Mg).