Display panel and display device with virtual pixel circuit electrically connected to light emitting device in display area

1. A display panel, comprising:

a base substrate, comprising a display area and a peripheral area surrounding the display area, wherein the display area comprises a first display area and a second display area;

a plurality of pixel circuits, comprising a plurality of virtual pixel circuits and a plurality of drive pixel circuits, wherein the plurality of virtual pixel circuits are arranged in the peripheral area, and the plurality of drive pixel circuits are arranged in the second display area;

a plurality of light emitting devices, arranged on a side, facing away from the base substrate, of the plurality of pixel circuits, wherein the plurality of light emitting devices comprise a plurality of first light emitting devices and a plurality of second light emitting devices, the plurality of first light emitting devices are arranged in the first display area, and the plurality of second light emitting devices are arranged in the second display area;

wherein at least one of the plurality of virtual pixel circuits is electrically connected with at least one of the plurality of first light emitting devices, and at least one of the plurality of drive pixel circuits is electrically connected with at least one of the plurality of second light emitting devices;

the peripheral area comprises a first peripheral sub-area and a second peripheral sub-area which are arranged oppositely, and a third peripheral sub-area and a fourth peripheral sub-area which are arranged oppositely;

the first peripheral sub-area, the first display area and the second peripheral sub-area are arranged along a first direction, and the third peripheral sub-area, the first display area and the fourth peripheral sub-area are arranged along a second direction, wherein the first direction is different from the second direction; and

the plurality of virtual pixel circuits are arranged in at least one of the first peripheral sub-area, the second peripheral sub-area, the third peripheral sub-area and the fourth peripheral sub-area, and the at least one of the plurality of virtual pixel circuits is electrically connected with the at least one of the plurality of first light emitting devices through at least one connecting trace.

2. The display panel according to claim 1 , wherein the plurality of first light emitting devices are arranged in the first display area in an array, and the plurality of second light emitting devices are arranged in the second display area in an array, wherein a row of the plurality of first light emitting devices and a row of the plurality of second light emitting devices are arranged in the same row; and/or, a column of the plurality of first light emitting devices and a column of the plurality of second light emitting devices are arranged in the same column.

3. The display panel according to claim 2 , wherein a distance between the first peripheral sub-area and the first display area is less than a distance between the second peripheral sub-area and the first display area, and the plurality of virtual pixel circuits are arranged in the first peripheral sub-area.

4. The display panel according to claim 3 , wherein the first peripheral sub-area comprises a plurality of first virtual areas which are arranged along the second direction, and the plurality of virtual pixel circuits are respectively arranged in an array in each of the plurality of first virtual areas;

the plurality of first light emitting devices are divided into a plurality of first row groups; and each of the plurality of first row groups comprises at least two adjacent rows of the plurality of first light emitting devices; and

one of the plurality of first row groups corresponds to one of the plurality of first virtual areas, and one of the plurality of first light emitting devices in the one of the plurality of first row groups is electrically connected with one of the plurality of virtual pixel circuits in the corresponding one of the plurality of first virtual areas through the at least one connecting trace.

5. The display panel according to claim 4 , wherein the one of the plurality of first row groups comprises a first sub-row group and a second sub-row group; the first display area has a first center line along the first direction, and the plurality of first light emitting devices in the first sub-row group and the plurality of first light emitting devices in the second sub-row group are symmetrically arranged with respect to the first center line;

the one of the plurality of first virtual areas comprises a first sub-virtual area and a second sub-virtual area; wherein the first sub-virtual area and the second sub-virtual area are symmetrically arranged with respect to the first center line, and the first sub-row group and the first sub-virtual area are arranged on the same side of the first center line;

the one of the plurality of first light emitting devices in the first sub-row group is electrically connected with the one of the plurality of virtual pixel circuits in the first sub-virtual area through the connecting trace; and

the one of the plurality of first light emitting devices in the second sub-row group is electrically connected with the one of the plurality of virtual pixel circuits in the second sub-virtual area through the connecting trace.

6. The display panel according to claim 5 , wherein in the same one of the plurality of first row groups, connecting traces corresponding to the first sub-row group and connecting traces corresponding to the second sub-row group are symmetrically arranged with respect to the first center line.

7. The display panel according to claim 5 , wherein the second display area further comprises a plurality of drive gate lines and a plurality of drive data lines; a row of the plurality of drive pixel circuits are electrically connected with one of the plurality of drive gate lines, and a column of the plurality of drive pixel circuits are electrically connected with one of the plurality of drive data lines;

the first sub-virtual area further comprises: a plurality of first sub-virtual gate lines and a plurality of first sub-virtual data lines; wherein in the first sub-virtual area, a row of the plurality of virtual pixel circuits are electrically connected with one of the plurality of first sub-virtual gate lines, and a column of the plurality of virtual pixel circuits are electrically connected with one of the plurality of first sub-virtual data lines;

the second sub-virtual area further comprises: a plurality of second sub-virtual gate lines and a plurality of second sub-virtual data lines; wherein in the second sub-virtual area, a row of the plurality of virtual pixel circuits are electrically connected with one of the plurality of second sub-virtual gate lines, and a column of the plurality of virtual pixel circuits are electrically connected with one of the plurality of second sub-virtual data lines;

for the plurality of first light emitting devices and the plurality of second light emitting devices in the same row, a drive signal transmitted by the one of the plurality of first sub-virtual gate lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, a drive signal transmitted by the one of the plurality of second sub-virtual gate lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and a drive signal transmitted by the one of the plurality of drive gate lines electrically connected with the at least one of the plurality of drive pixel circuits corresponding to the at least one of the plurality of second light emitting devices are the same; and

for the plurality of first light emitting devices and the plurality of second light emitting devices in the same column, the one of the plurality of first sub-virtual data lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, the one of the plurality of second sub-virtual data lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and the one of the plurality of drive data lines electrically connected with the at least one of the plurality of drive pixel circuits corresponding to the at least one of the plurality of second light emitting devices are electrically connected with each other.

8. The display panel according to claim 7 , wherein the peripheral area further comprises: a gate drive circuit electrically connected with the plurality of drive gate lines, wherein the gate drive circuit is configured to input the drive signals to the plurality of drive gate lines, and for the plurality of first light emitting devices and the plurality of second light emitting devices in the same row, the one of the plurality of first sub-virtual gate lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and the one of the plurality of second sub-virtual gate lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices are electrically connected with the one of the plurality of drive gate lines which is electrically connected with the at least one of the plurality of drive pixel circuits corresponding to the at least one of the plurality of second light emitting devices; or,

the peripheral area further comprises: a gate drive circuit electrically connected with the the peripheral area further comprises: a gate drive circuit electrically connected with the plurality of drive gate lines, a first virtual gate drive circuit electrically connected with the plurality of first sub-virtual gate lines, and a second virtual gate drive circuit electrically connected with the plurality of second sub-virtual gate lines; wherein the gate drive circuit is configured to input the drive signals to the plurality of drive gate lines, the first virtual gate drive circuit is configured to input the drive signals to the plurality of first sub-gate lines, and the second virtual gate drive circuit is configured to input the drive signals to the plurality of second sub-gate lines.

9. The display panel according to claim 1 , wherein part of the plurality of virtual pixel circuits are arranged in the third peripheral sub-area, and the rest of the plurality of virtual pixel circuits are arranged in the fourth peripheral sub-area.

10. The display panel according to claim 9 , wherein the second display area further comprises a plurality of drive gate lines and a plurality of drive data lines; wherein a row of the plurality of drive pixel circuits are electrically connected with one of the plurality of drive gate lines, and a column of the plurality of drive pixel circuits are electrically connected with one of the plurality of drive data lines;

the third peripheral sub-area further comprises: a plurality of second virtual gate lines and a plurality of second virtual data lines; wherein in the third peripheral sub-area, a row of the plurality of virtual pixel circuits are electrically connected with one of the plurality of second virtual gate lines, and a column of the plurality of virtual pixel circuits are electrically connected with one of the plurality of second virtual data lines;

the fourth peripheral sub-area further comprises: a plurality of third virtual gate lines and a plurality of third virtual data lines; wherein in the fourth peripheral sub-area, a row of the plurality of virtual pixel circuits are electrically connected with one of the plurality of third virtual gate lines, and a column of the plurality of virtual pixel circuits are electrically connected with one of the plurality of third virtual data lines;

for the plurality of first light emitting devices and the plurality of second light emitting devices in the same row, a drive signal transmitted by the one of the plurality of second virtual gate lines electrically connected with the at least one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, a drive signal transmitted by the one of the plurality of third virtual gate lines electrically connected with the at least one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and a drive signal transmitted by the one of the plurality of drive gate lines electrically connected with the at least one of the plurality of drive pixel circuits of the corresponding at least one of the plurality of second light emitting devices are the same; and

for the plurality of first light emitting devices and the plurality of second light emitting devices in the same column, the one of the plurality of second virtual data lines electrically connected with the at least one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, the one of the plurality of third virtual data lines electrically connected with the at least one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and the one of the plurality of drive data lines electrically connected with the at least one of the plurality of drive pixel circuits corresponding to the at least one of the plurality of second light emitting devices are electrically connected with each other.

11. The display panel according to claim 10 , wherein the peripheral area further comprises: a gate drive circuit electrically connected with the plurality of drive gate lines, wherein the gate drive circuit is configured to input the drive signals to the plurality of drive gate lines, and for the plurality of first light emitting devices and the plurality of second light emitting devices in the same row, the one of the plurality of second virtual gate lines electrically connected with the at least one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, the one of the plurality of third virtual gate lines electrically connected with the at least one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and the one of the plurality of drive gate lines electrically connected with the at least one of the plurality of drive pixel corresponding to the at least one of the plurality of second light emitting devices are the same gate line; or, circuits

the peripheral area further comprises: a gate drive circuit electrically connected with the plurality of drive gate lines, a second virtual gate drive circuit electrically connected with the plurality of second virtual gate lines and a third virtual gate drive circuit electrically connected with the plurality of third virtual gate lines, wherein the gate drive circuit is configured to input the drive signals to the plurality of drive gate lines, the second virtual gate drive circuit is configured to input the drive signals to the plurality of second virtual gate lines, and the third virtual gate drive circuit is configured to input the drive signals to the plurality of third virtual gate lines.

12. A display device, comprising the display panel according to claim 1 .

13. The display device according to claim 12 , wherein the plurality of first light emitting devices are arranged in the first display area in an array, and the plurality of second light emitting devices are arranged in the second display area in an array, wherein a row of the plurality of first light emitting devices and a row of the plurality of second light emitting devices are arranged in the same row; and/or, a column of the plurality of first light emitting devices and a column of the plurality of second light emitting devices are arranged in the same column.

14. The display device according to claim 12 , wherein a distance between the first peripheral sub-area and the first display area is less than the distance between the second peripheral sub-area and the first display area, and the plurality of virtual pixel circuits are arranged in the first peripheral sub-area.

15. The display device according to claim 14 , wherein the first peripheral sub-area comprises a plurality of first virtual areas which are arranged along the second direction, and the plurality of virtual pixel circuits are respectively arranged in an array in each of the plurality of first virtual areas;

the plurality of first light emitting devices are divided into a plurality of first row groups; and each of the plurality of first row groups comprises at least two adjacent rows of the plurality of first light emitting devices; and

one of the plurality of first row groups corresponds to one of the plurality of first virtual areas, and one of the plurality of first light emitting devices in the one of the plurality of first row groups is electrically connected with one of the plurality of virtual pixel circuits in the corresponding one of the plurality of first virtual areas through the at least one connecting trace.

16. The display device according to claim 15 , wherein the one of the plurality of first row groups comprises a first sub-row group and a second sub-row group; the first display area has a first center line along the first direction, and the plurality of first light emitting devices in the first sub-row group and the plurality of first light emitting devices in the second sub-row group are symmetrically arranged with respect to the first center line;

the one of the plurality of first virtual areas comprises a first sub-virtual area and a second sub-virtual area; wherein the first sub-virtual area and the second sub-virtual area are symmetrically arranged with respect to the first center line, and the first sub-row group and the first sub-virtual area are arranged on the same side of the first center line;

the one of the plurality of first light emitting devices in the first sub-row group is electrically connected with the one of the plurality of virtual pixel circuits in the first sub-virtual area through the connecting trace; and

the one of the plurality of first light emitting devices in the second sub-row group is electrically connected with the one of the plurality of virtual pixel circuits in the second sub-virtual area through the connecting trace.

17. The display device according to claim 16 , wherein in the same one of the plurality of first row groups, connecting traces corresponding to the first sub-row group and connecting traces corresponding to the second sub-row group are symmetrically arranged with respect to the first center line.

18. The display device according to claim 16 , wherein the second display area further comprises a plurality of drive gate lines and a plurality of drive data lines; a row of the plurality of drive pixel circuits are electrically connected with one of the plurality of drive gate lines, and a column of the plurality of drive pixel circuits are electrically connected with one of the plurality of drive data lines;

the first sub-virtual area further comprises: a plurality of first sub-virtual gate lines and a plurality of sub-virtual data lines; wherein in the first sub-virtual area, a row of the plurality of virtual pixel circuits are electrically connected with one of the plurality of first sub-virtual gate lines, and a column of the plurality of virtual pixel circuits are electrically connected with one of the plurality of first sub-virtual data lines;

the second sub-virtual area further comprises: a plurality of second sub-virtual gate lines and a plurality of second sub-virtual data lines; wherein in the second sub-virtual area, a row of the plurality of virtual pixel circuits are electrically connected with one of the plurality of second sub-virtual gate lines, and a column of the plurality of virtual pixel circuits are electrically connected with one of the plurality of second sub-virtual data lines;

for the plurality of first light emitting devices and the plurality of second light emitting devices in the same row, a drive signal transmitted by the one of the plurality of first sub-virtual gate lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, a drive signal transmitted by the one of the plurality of second sub-virtual gate lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and a drive signal transmitted by the one of the plurality of drive gate lines electrically connected with the at least one of the plurality of drive pixel circuits corresponding to the at least one of the plurality of second light emitting devices are the same; and

for the plurality of first light emitting devices and the plurality of second light emitting devices in the same column, the one of the plurality of first sub-virtual data lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, the one of the plurality of second sub-virtual data lines electrically connected with the one of the plurality of virtual pixel circuits corresponding to the at least one of the plurality of first light emitting devices, and the one of the plurality of drive data lines electrically connected with the at least one of the plurality of drive pixel circuits corresponding to the at least one of the plurality of second light emitting devices are electrically connected with each other.