Signal encoding method and a semiconductor device to generate an optimal transition code in a multi-level signaling system

1. A signal processing method of a semiconductor device, the method comprising:

receiving, at an encoder of the semiconductor device, a first digital code of a first digital signal;

generating, at the encoder, a constraint vector, wherein the constraint vector is a signal based on comparing at least one least significant bit (LSB) of the first digital code with a second digital code, which is a previous digital code with respect to the first digital code, to indicate a position where a maximum transition code is able to occur in the first digital code;

masking, at the encoder, the first digital code with a transmitting mask based on the constraint vector; and

outputting, from the encoder, the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.

2. The signal processing method of claim 1 , wherein the first digital code is based on gray coding of a pulse amplitude modulation of four or more levels.

3. The signal processing method of claim 1 , wherein the transmitting mask includes a plurality of transmitting masks corresponding to a bit number of the first digital code.

4. The signal processing method of claim 3 , wherein the transmitting mask that masks the first digital code is a mask in which the sum of bit counts calculated corresponding to the constraint vector and the first digital code is the maximum, among the plurality of transmitting masks.

5. The signal processing method of claim 4 , wherein the bit count is the number of positions where the maximum transition code is able to occur in the first digital code.

6. The signal processing method of claim 3 , wherein the DBI bit is a digital code corresponding to each of the plurality of masks.

7. The signal processing method of claim 1 , wherein the transmitting mask includes a plurality of transmitting mask books, each transmitting mask book including a plurality of transmitting masks corresponding to a bit number of the first digital code.

8. The signal processing method of claim 1 , wherein a receiving semiconductor device that communicates with a transmitting semiconductor device receives the masked first digital code and the DBI bit;

selects a receiving mask corresponding to the DBI bit; and

unmasks the masked first digital code with the selected receiving mask.

9. The signal processing method of claim 8 , wherein the receiving mask is selected among a plurality of receiving masks, on the basis of the DBI bit and another constraint vector generated from a second digital code which is a previous digital code with respect to the first digital code.

10. A semiconductor device, comprising:

a processing unit which outputs a first digital code;

an encoder which masks the first digital code with a transmitting mask based on a constraint vector, wherein the constraint vector is signal based on comparing at least one least significant bit (LSB) of the first digital code with the second digital code to indicate a position where a maximum transition code is able to occur in the first digital code; and

a transmitting circuit which transmits the masked first digital code and a Data Bus Inversion (DBI) bit of the transmitting mask,

wherein the constraint vector is based on a second digital code which is a previous digital code with respect to the first digital code.

11. The semiconductor device of claim 10 , wherein the encoder comprises:

a register which stores the second digital code;

a constraint vector calculator which generates the constraint vector on the basis of the second digital code;

a mask selector which stores a plurality of transmitting masks and outputs the transmitting mask corresponding to the constraint vector; and

an operating unit which masks the first digital code with the transmitting mask output from the mask selector.

12. The semiconductor device of claim 11 , wherein the DBI bit has a plurality of code values corresponding to each of the plurality of transmitting masks.

13. The semiconductor device of claim 11 , further comprising:

a mask book selector which stores a plurality of transmitting mask books and selects any one transmitting mask book corresponding to the constraint vector.

14. The semiconductor device of claim 13 , wherein the plurality of mask books include the plurality of transmitting masks, and

the mask book selector outputs any one transmitting mask from the transmitting mask book selected to correspond to the constraint vector.

15. The semiconductor device of claim 11 , wherein the transmitting mask output by the mask selector is a mask in which the sum of bit counts calculated corresponding to the constraint vector and the first digital code is the maximum, among the plurality of transmitting masks.

16. The semiconductor device of claim 10 , wherein the semiconductor device is included in each of a memory controller and a memory device.

17. A semiconductor device, comprising:

a receiving circuit which receives a first digital code and a Data Bus Inversion (DBI) bit; and

a decoder which unmasks the first digital code with a receiving mask based on the DBI bit,

wherein the receiving mask corresponds to a constraint vector generated on the basis of a second digital code which is a previous digital code with respect to the first digital code,

wherein the decoder includes:

a receiving mask book selector which stores a plurality of receiving mask books and selects any one receiving mask book corresponding to the constraint vector,

wherein a mask selector outputs the receiving mask corresponding to the DBI bit in the selected receiving mask book.

18. The semiconductor device of claim 17 , wherein the decoder includes:

a register which stores the second digital code;

a constraint vector calculator which generates the constraint vector on the basis of the second digital code;

the mask selector which stores a plurality of receiving masks and outputs the receiving mask corresponding to the DBI bit; and

an operating unit which unmasks the first digital code with the receiving mask output from the mask selector.

19. The semiconductor device of claim 17 , wherein the semiconductor device is included in each of a memory controller and a memory device.