Integrated circuit devices with receiver chain peak detectors
An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.
1. An integrated circuit comprising:
an amplifier having a first input, a control input, and an output;
a first path having an output, the first path including a first mixer having an input coupled to the output of the amplifier;
a second path having an output, the second path including a second mixer having an input coupled to the first path; and
a control circuit having a first input coupled to the output of the first path, having a second input coupled to the output of the second path, and having a control output coupled to the control input of the amplifier, wherein the control circuit is configured to:
receive, at the second input, a first signal representative of an interference component and a data component of a received signal;
receive at the first input, a second signal representative of the data component without the interference component; and
provide, at the control output, a control signal based on the first and second signals, wherein a bandwidth of the first mixer reduces the interference component, and a bandwidth of the second mixer passes the interference component.
2. The integrated circuit of claim 1 , wherein the first mixer has a control input coupled to the control output, and has an output.
3. The integrated circuit of claim 2 , wherein the first path further includes:
a filter having a first input, a control input, and an output, the first input of the filter coupled to the output of the first mixer, the control input of the filter coupled to the control output; and
an analog-to-digital converter (ADC) having an input and an output, the input of the ADC coupled to the output of the filter, the output of the ADC coupled to the first input of the control circuit.
4. The integrated circuit of claim 1 , wherein the second path further includes:
a peak detector having an input and an output, the input of the peak detector coupled to an output of the second mixer; and
an analog-to-digital converter (ADC) having an input and an output, the input of the ADC coupled to the output of the peak detector, the output of the ADC coupled to the second input of the control circuit.
5. The integrated circuit of claim 4 , wherein:
the peak detector includes:
a diode having an anode and a cathode, the anode coupled to the output of the second mixer; and
a capacitor having a first terminal and a second terminal, the first terminal coupled to the cathode, the second terminal coupled to a ground terminal.
6. The integrated circuit of claim 4 , wherein:
the output of the second mixer is a differential output including a first mixer output and a second mixer output.
7. The integrated circuit of claim 1 , wherein the input of the second mixer is coupled to the output of the amplifier.
8. The integrated circuit of claim 1 , wherein the input of the second mixer is coupled to the first input of the amplifier.
9. The integrated circuit of claim 1 , further comprising:
an antenna coupled to the first input of the amplifier.
10. The integrated circuit of claim 1 , wherein:
a bandwidth of the second mixer is wider than a bandwidth of the first mixer.
11. The integrated circuit of claim 1 , wherein the control circuit is configured to limit a maximum gain of the first path based on the first signal.
12. The integrated circuit of claim 1 , wherein the control circuit comprises an automatic gain control (AGC) circuit.
13. An integrated circuit comprising:
an amplifier having a first input, a control input, and an output;
a first path having an output, the first path including a first mixer having an input coupled to the output of the amplifier;
a second path comprising:
an output,
a second mixer having an input coupled to the first path,
a peak detector having an input and an output, the input of the peak detector coupled to an output of the second mixer, and
an analog-to-digital converter (ADC) having an input and an output, the input of the ADC coupled to the output of the peak detector; and
a control circuit having a first input coupled to the output of the first path, a second input coupled to the output of the second path, and a control output coupled to the control input of the amplifier, wherein the output of the ADC is coupled to the second input of the control circuit, and wherein the control circuit is configured to:
receive, at the second input, a first signal representative of an interference component and a data component of a received signal;
receive at the first input, a second signal representative of the data component without the interference component; and
provide, at the control output, a control signal based on the first and second signals, wherein the peak detector includes:
a first transistor having a first control terminal coupled to the second mixer, having a first current terminal, and having a second current terminal; and
a second transistor having a second control terminal coupled to the second mixer, having a third current terminal, and having a fourth current terminal.
14. The integrated circuit of claim 13 , wherein:
the first current terminal and the third current terminal are coupled to a voltage source terminal;
the second current terminal and the fourth current terminal are coupled to a first current source, a first capacitor and a first resistor; and
the first resistor is coupled to a second capacitor and to the input of the ADC.
15. The integrated circuit of claim 14 , wherein the peak detector further includes:
a third transistor having a third control terminal coupled to a common mode voltage terminal, having a fifth current terminal, and having a sixth current terminal; and
a fourth transistor having a fourth control terminal coupled to the common mode voltage terminal, having a seventh current terminal, and having an eighth current terminal.
16. The integrated circuit of claim 15 , wherein:
the fifth current terminal and the seventh current terminal are coupled to the voltage source terminal;
the sixth current terminal and the eighth current terminal are coupled to a second current source, a third capacitor and a second resistor; and
the second resistor is coupled to a fourth capacitor and to the input of the ADC.
17. The integrated circuit of claim 13 , wherein a bandwidth of the first mixer reduces the interference component, and a bandwidth of the second mixer passes the interference component.
18. The integrated circuit of claim 13 , wherein the control circuit comprises an automatic gain control (AGC) circuit.
19. The integrated circuit of claim 13 , wherein the output of the second mixer is a differential output.
20. Circuitry comprising:
an amplifier having a first input, a first control input, and an output;
a first path including:
a first mixer having a first input coupled to the output of the amplifier, having a second control input, and having an output;
a filter having a first input coupled to the output of the first mixer, having a third control input, and having an output; and
a first analog-to-digital converter (ADC) having an input coupled to the output of the filter, and having an output;
a second path including:
a second mixer having an input coupled to the first input of the amplifier, and having an output;
a peak detector having an input coupled to the output of the second mixer, and having an output; and
a second ADC having an input coupled to the output of the peak detector, and having an output; and
a control circuit having a first input coupled to the output of the first ADC and configured to receive a first signal, having a second input coupled to the output of the second ADC and configured to receive a second signal, and having a control output coupled to the first, second, and third control inputs, wherein the control circuit is configured to provide, at the control output, a control signal based on the first and second signals, wherein the peak detector includes:
a first transistor having a first control terminal coupled to the second mixer, having a first current terminal, and having a second current terminal;
a second transistor having a second control terminal coupled to the second mixer, having a third current terminal coupled to the first current terminal, and having a fourth current terminal coupled to the second current terminal;
a current source having a first terminal coupled to the second and fourth current terminals, and having a second terminal;
a first capacitor having a first terminal coupled to the second and fourth current terminals, and having a second terminal coupled to the second terminal of the current source;
a resistor having a first terminal coupled to the second and fourth current terminals, and having a second terminal coupled to the input of the second ADC; and
a second capacitor having a first terminal coupled to the input of the second ADC, and having a second terminal coupled to the second terminals of the current source and the first capacitor.
21. The circuitry of claim 20 , wherein the second signal is representative of an interference component and a data component of a received signal; and the first signal is representative of the data component without the interference component.
22. The circuitry of claim 21 , wherein a bandwidth of the first mixer reduces the interference component, and a bandwidth of the second mixer passes the interference component.