IP Library › Granted Patent US 11,824,683
Granted Patent B2
US 11,824,683 · App. 17/657,081 · Granted Nov 21, 2023

Data processing unit for compute nodes and storage nodes

Inventors: Pradeep Sindhu (Los Altos Hills, CA); Jean-Marc Frailong (Rancho Mirage, CA); Bertrand Serlet (Palo Alto, CA); Wael Noureddine (Santa Clara, CA); Felix A. Marti (San Francisco, CA); Deepak Goel (San Jose, CA); Rajan Goyal (Saratoga, CA)
Assignee: Microsoft Technology Licensing, LLC
H04L12/4633G06F9/546G06F12/0817G06F13/1668G06F13/4282H04L12/56H04L45/02H04L49/10H04L49/253G06F12/0811G06F2212/1024G06F2212/152G06F2213/0026H04L2012/5619H04L2012/5681
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Quick Facts
Patent No.
US 11,824,683
App. No.
17/657,081
Granted
Nov 21, 2023
Kind
B2
Abstract

A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.

Claims (28)

1. A data processing unit configurable for communicatively coupling to one or more storage devices and to one or more application processors, the data processing unit comprising:

a plurality of programmable processing cores configured to perform processing tasks on packet-based data, wherein, to perform the processing tasks, one of the plurality of programmable processing cores is configured to execute a work unit function to process a work unit associated with a portion of the packet-based data, wherein the work unit comprises a data structure that includes a pointer to the portion of the packet-based data in memory, a first identifier that specifies the work unit function for processing the portion of the packet-based data, and a second identifier that specifies the one of the plurality of programmable processing cores included in the data processing unit for executing the work unit function; and

one or more interfaces configured to communicate the packet-based data between the data processing unit and one or more of a network, the storage devices, or the application processors based at least on one or more of the pointer, the first identifier, and the second identifier.

2. The data processing unit of claim 1 , wherein the one or more interfaces include at least one network interface, the data processing unit further comprising a networking unit including the at least one network interface, the networking unit configured to control communication of the packet-based data between the data processing unit and the network over the at least one network interface.

3. The data processing unit of claim 2 , wherein the at least one network interface includes at least one Ethernet interface, wherein the networking unit is configured to support the at least one Ethernet interface to connect directly to the network without a separate network interface card (NIC).

4. The data processing unit of claim 1 , wherein the one or more interfaces include at least one host interface, the data processing unit further comprising at least one host unit including the at least one host interface, the at least one host unit configured to control communication of the packet-based data between the data processing unit and at least one of the one or more storage devices over the at least one host interface.

5. The data processing unit of claim 4 , wherein the at least one host interface includes at least one PCI-e (Peripheral Component Interconnect-Express) interface, wherein the at least one host unit is configured to support the at least one PCI-e interface to connect directly to the at least one of the one or more storage devices.

6. The data processing unit of claim 1 , wherein the one or more interfaces include at least one host interface, the data processing unit further comprising at least one host unit including the at least one host interface, the at least one host unit configured to control communication of the packet-based data between the data processing unit and at least one of the one or more application processors over the at least one host interface.

7. The data processing unit of claim 6 , wherein the at least one host interface includes at least one PCI-e (Peripheral Component Interconnect-Express) interface, wherein the at least one host unit is configured to support the at least one PCI-e interface to connect directly to the at least one of the one or more application processors.

8. The data processing unit of claim 1 ,

wherein the data processing unit communicatively couples to the one or more storage devices and the one or more application processors via respective system bus connections; and

wherein the one or more interfaces are configured to communicate the packet-based data to the respective system bus connections to one or more of the storage devices or the application processors.

9. The data processing unit of claim 1 , wherein at least one of the application processors comprises a central processing unit (CPU), and wherein the data processing unit is positioned between and communicatively coupled to the CPU and the storage devices, wherein the data processing unit is configured to retrieve the data from the storage devices on behalf of the CPU, store the data to the storage devices on behalf of the CPU, and retrieve the data from the network on behalf of the CPU.

10. The data processing unit of claim 1 , wherein at least one of the application processors comprises a graphics processing unit (GPU), and wherein the data processing unit is positioned between and communicatively coupled to the GPU and the storage devices, wherein the data processing unit is configured to feed the data from at least one of the network or the storage devices to the GPU for processing.

11. A device comprising at least one data processing unit configurable for communicatively coupling to one or more storage devices and to one or more application processors, the data processing unit configured to:

perform processing tasks on packet-based data, wherein, to perform the processing tasks, the data processing unit is configured to execute a work unit function to process a work unit associated with a portion of the packet-based data, wherein the work unit comprises a data structure that includes a pointer to the portion of the packet-based data in memory, a first identifier that specifies the work unit function for processing the portion of the packet-based data, and a second identifier that specifies one of a plurality of programmable processing cores included in the data processing unit for executing the work unit function, and

control communication of the packet-based data between the data processing unit and one or more of a network, the storage devices, or the application processors based at least on one or more of the pointer, the first identifier, and the second identifier.

12. The device of claim 11 , wherein the data processing unit comprises a networking unit including at least one network interface, the networking unit configured to control communication of the packet-based data between the data processing unit and the network over the at least one network interface.

13. The device of claim 11 , wherein the data processing unit further comprises at least one host unit including at least one host interface, the at least one host unit configured to control communication of the packet-based data between the data processing unit and at least one of the one or more storage devices over the at least one host interface.

14. The device of claim 11 , wherein the data processing unit further comprises at least one host unit including at least one host interface, the at least one host unit configured to control communication of the packet-based data between the data processing unit and at least one of the one or more application processors over the at least one host interface.

15. The device of claim 11 ,

wherein the data processing unit communicatively couples to the one or more storage devices and the one or more application processors via respective system bus connections; and

wherein the one or more interfaces are configured to communicate the packet-based data to the respective system bus connections to one or more of the storage devices or the application processors.

16. The device of claim 11 , wherein at least one of the application processors comprises a central processing unit (CPU), and wherein the data processing unit is positioned between and communicatively coupled to the CPU and the storage devices, wherein the data processing unit is configured to retrieve the data from the storage devices on behalf of the CPU, store the data to the storage devices on behalf of the CPU, and retrieve the data from the network on behalf of the CPU.

17. The device of claim 11 , wherein at least one of the application processors comprises a graphics processing unit (GPU), and wherein the data processing unit is positioned between and communicatively coupled to the GPU and the storage devices, wherein the data processing unit is configured to feed the data from at least one of the network or the storage devices to the GPU for processing.

18. The device of claim 11 , wherein the device includes the at least one data processing unit and at least one of the one or more storage devices.

19. The device of claim 11 , wherein the device includes the at least one data processing unit and at least one of the one or more application processors.

20. The device of claim 11 , wherein the device includes the at least one data processing unit, at least one of the one or more application processors, and at least one of the one or more storage devices.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2023
From: FUNGIBLE, INC.
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 064434/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2023
From: SINDHU, PRADEEP; FRAILONG, JEAN-MARC; SERLET, BERTRAND; NOUREDDINE, WAEL; MARTI, FELIX A.; GOEL, DEEPAK; GOYAL, RAJAN
To: FUNGIBLE, INC.
Reel/Frame 063580/0151 →
Continuity (4)
Continuation 16031921 · Jul 10, 2018
Provisional Application 62559021 · Sep 15, 2017
Provisional Application 62530691 · Jul 10, 2017
Related Publication 20220224564A1 · Jul 14, 2022
Cited By (1)
US 12,536,036