Directed interrupt virtualization with fallback
A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.
1. A computer program product for facilitating processing within a computing environment, the computer program product comprising:
one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising:
receiving, by a processor of the computing environment, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor; and
broadcasting to one or more other processors of the computing environment the interrupt signal to be handled, based on the checking indicating that the interrupt target ID received with the interrupt signal does not match the current interrupt target ID assigned to the processor.
2. The computer program product of claim 1 , wherein the computing environment includes a plurality of processors assigned for usage by a guest operating system, the plurality of processors including the processor receiving the interrupt signal, and wherein the method further comprises broadcasting, based on the checking being unsuccessful, the interrupt signal to remaining processors of the plurality of processors for handling of the interrupt signal by the guest operating system, the remaining processors including the one or more other processors.
3. The computer program product of claim 2 , wherein the receiving the interrupt signal further comprises receiving the interrupt signal with an interrupt subclass ID identifying an interrupt subclass to which the interrupt signal is assigned, and wherein the broadcasting is limited to the remaining processors assigned to the interrupt subclass ID.
4. The computer program product of claim 1 , wherein the method further comprises:
receiving, by the processor, another interrupt signal, wherein the another interrupt signal is received with another interrupt target ID identifying the target processor for handling the another interrupt signal;
checking whether the processor is the target processor identified by the another interrupt target ID, the checking comprising performing the comparison of the another interrupt target ID with the current interrupt target ID assigned to the processor; and
accepting, based on the checking being successful, the another interrupt signal for handling by the processor.
5. The computer program product of claim 4 , wherein the processor is assigned for usage by a guest operating system, and wherein the receiving the another interrupt signal further comprises receiving the another interrupt signal with a logical partition ID identifying a logical partition to which the guest operating system is assigned, and wherein the checking further comprises comparing the logical partition ID with a current logical partition ID assigned to the processor, wherein the accepting further comprises performing the accepting based on the checking being successful.
6. The computer program product of claim 5 , wherein the computing environment includes a plurality of processors assigned for usage by the guest operating system, the plurality of processors including the processor receiving the another interrupt signal, and wherein the method further comprises broadcasting, based on the checking being unsuccessful, the another interrupt signal to remaining processors of the plurality of processors for handling of the another interrupt signal by the guest operating system.
7. The computer program product of claim 6 , wherein the broadcasting is limited to the remaining processors of the plurality of processors assigned to the logical partition ID.
8. The computer program product of claim 4 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the another interrupt target ID is scheduled for usage by a guest operating system of the computing environment, based on an interrupt blocking indicator indicating that the target processor identified by the another interrupt target ID is currently not blocked from receiving interrupt signals, and based on a direct signaling indicator indicating that the target processor is to be addressed directly.
9. The computer program product of claim 1 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the interrupt target ID is scheduled for usage by a guest operating system of the computing environment.
10. The computer program product of claim 1 , wherein the receiving is performed based on an interrupt blocking indicator indicating that the target processor identified by the interrupt target ID is currently not blocked from receiving interrupt signals.
11. The computer program product of claim 1 , wherein the receiving is performed based on a direct signaling indicator indicating that the target processor is to be addressed directly.
12. A computer system for facilitating processing within a computing environment, the computer system comprising:
a memory; and
at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
receiving, by a processor of the computing environment, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor; and
broadcasting to one or more other processors of the computing environment the interrupt signal to be handled, based on the checking indicating that the interrupt target ID received with the interrupt signal does not match the current interrupt target ID assigned to the processor.
13. The computer system of claim 12 , wherein the computing environment includes a plurality of processors assigned for usage by a guest operating system, the plurality of processors including the processor receiving the interrupt signal, and wherein the method further comprises broadcasting, based on the checking being unsuccessful, the interrupt signal to remaining processors of the plurality of processors for handling of the interrupt signal by the guest operating system, the remaining processors including the one or more other processors.
14. The computer system of claim 13 , wherein the receiving the interrupt signal further comprises receiving the interrupt signal with an interrupt subclass ID identifying an interrupt subclass to which the interrupt signal is assigned, and wherein the broadcasting is limited to the remaining processors assigned to the interrupt subclass ID.
15. The computer system of claim 12 , wherein the method further comprises:
receiving, by the processor, another interrupt signal, wherein the another interrupt signal is received with another interrupt target ID identifying the target processor for handling the another interrupt signal;
checking whether the processor is the target processor identified by the another interrupt target ID, the checking comprising performing the comparison of the another interrupt target ID with the current interrupt target ID assigned to the processor; and
accepting, based on the checking being successful, the another interrupt signal for handling by the processor.
16. The computer system of claim 15 , wherein the processor is assigned for usage by a guest operating system, and wherein the receiving the another interrupt signal further comprises receiving the another interrupt signal with a logical partition ID identifying a logical partition to which the guest operating system is assigned, and wherein the checking further comprises comparing the logical partition ID with a current logical partition ID assigned to the processor, wherein the accepting further comprises performing the accepting based on the checking being successful.
17. The computer system of claim 16 , wherein the computing environment includes a plurality of processors assigned for usage by the guest operating system, the plurality of processors including the processor receiving the another interrupt signal, and wherein the method further comprises broadcasting, based on the checking being unsuccessful, the another interrupt signal to remaining processors of the plurality of processors for handling of the another interrupt signal by the guest operating system, and wherein the broadcasting is limited to the remaining processors of the plurality of processors assigned to the logical partition ID.
18. The computer system of claim 15 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the another interrupt target ID is scheduled for usage by a guest operating system of the computing environment, based on an interrupt blocking indicator indicating that the target processor identified by the another interrupt target ID is currently not blocked from receiving interrupt signals, and based on a direct signaling indicator indicating that the target processor is to be addressed directly.
19. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:
receiving, by a processor of computing environment, an interrupt signal, the interrupt signal being received with an interrupt target ID identifying a target processor for handling the interrupt signal, the processor being a target of the interrupt signal directly;
checking whether the processor is the target processor identified by the interrupt target ID, the checking comprising performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor; and
broadcasting to one or more other processors of the computing environment the interrupt signal to be handled, based on the checking indicating that the interrupt target ID received with the interrupt signal does not match the current interrupt target ID assigned to the processor.
20. The computer-implemented method of claim 19 , wherein the computing environment includes a plurality of processors assigned for usage by a guest operating system, the plurality of processors including the processor receiving the interrupt signal, and further comprising broadcasting, based on the checking being unsuccessful, the interrupt signal to remaining processors of the plurality of processors for handling of the interrupt signal by the guest operating system, the remaining processors including the one or more other processors.
21. The computer-implemented method of claim 20 , wherein the receiving the interrupt signal further comprises receiving the interrupt signal with an interrupt subclass ID identifying an interrupt subclass to which the interrupt signal is assigned, and wherein the broadcasting is limited to the remaining processors assigned to the interrupt subclass ID.
22. The computer-implemented method of claim 19 , wherein the method further comprises:
receiving, by the processor, another interrupt signal, wherein the another interrupt signal is received with another interrupt target ID identifying the target processor for handling the another interrupt signal;
checking whether the processor is the target processor identified by the another interrupt target ID, the checking comprising performing the comparison of the another interrupt target ID with the current interrupt target ID assigned to the processor; and
accepting, based on the checking being successful, the another interrupt signal for handling by the processor.
23. The computer-implemented method of claim 22 , wherein the processor is assigned for usage by a guest operating system, and wherein the receiving the another interrupt signal further comprises receiving the another interrupt signal with a logical partition ID identifying a logical partition to which the guest operating system is assigned, and wherein the checking further comprises comparing the logical partition ID with a current logical partition ID assigned to the processor, wherein the accepting further comprises performing the accepting based on the checking being successful.
24. The computer-implemented method of claim 23 , wherein the computing environment includes a plurality of processors assigned for usage by the guest operating system, the plurality of processors including the processor receiving the another interrupt signal, and further comprising broadcasting, based on the checking being unsuccessful, the another interrupt signal to remaining processors of the plurality of processors for handling of the another interrupt signal by the guest operating system, and wherein the broadcasting is limited to the remaining processors of the plurality of processors assigned to the logical partition ID.
25. The computer-implemented method of claim 22 , wherein the receiving is performed based on a running indicator indicating that the target processor identified by the another interrupt target ID is scheduled for usage by a guest operating system of the computing environment, based on an interrupt blocking indicator indicating that the target processor identified by the another interrupt target ID is currently not blocked from receiving interrupt signals, and based on a direct signaling indicator indicating that the target processor is to be addressed directly.