Semiconductor device performing loop-back test operation

1. An apparatus comprising:

an external terminal;

an output buffer having a first input node, and the output buffer having an output node coupled to the external terminal;

an input receiver having an input node coupled to the external terminal and having an output node;

a multiplexer configured to select one of data supplied to the first input node of the output buffer and data output from the output node of the input receiver; and

a test read data path configured to bypass the output buffer, the input receiver, and the multiplexer.

2. The apparatus of claim 1 , wherein the multiplexer is configured to select the data supplied to the first input node of the output buffer in a first test operation and select the data output from the output node of the input receiver in a second test operation.

3. The apparatus of claim 2 , wherein the first test operation is performed at higher speed than the second test operation.

4. The apparatus of claim 1 , wherein the input receiver has an additional input node configured to receive a reference voltage.

5. The apparatus of claim 1 , wherein the test read data path comprises a comparator configured to receive, at a first input, test read data from a memory array.

6. The apparatus of claim 5 , wherein the comparator is further configured to receive a value from a test register, compare the test read data to the value, and generate a comparison result signal.

7. The apparatus of claim 6 , further comprising a test control circuit configured to receive the comparison result signal from the comparator and generate a pass/fail signal based on the comparison result signal.

8. The apparatus of claim 7 , wherein the pass/Tail signal indicates an operating status of the memory cell array, test read data path, or both.

9. The apparatus of claim 1 , further comprising a test path configured to bypass the output buffer and the input receiver.

10. A method comprising:

selecting, at a multiplexer, a first input node for a low-speed write test operation or a second input node for a high-speed write test operation, the second input node coupled to a test path configured to bypass another path coupled to the first input node;

writing test write data to a memory array; and

reading test read data from the memory array via a test read data path configured to bypass the test path, the other path, and the multiplexer.

11. The method of claim 10 , wherein the first input node for the low-speed test is selected at the multiplexer, and wherein writing the test write data to the memory array comprises:

outputting, by a test register, the test write data;

receiving, by the multiplexer at the first input node, the test write data;

latching, at a latch circuit, the test write data; and

providing, by the latch circuit, the test write data to the memory cell array.

12. The method of claim 11 , further comprising:

setting, by a test control circuit, the test write data into the test register.

13. The method of claim 10 , further comprising:

comparing, at a comparator, the test read data with a value received from a test register; and

outputting, at the comparator, a comparison result signal.

14. The method of claim 13 , further comprising:

outputting, by a test control circuit, a pass/fail signal based at least in part on the comparison result signal.

15. The method of claim 10 , wherein the second input node for the high-speed test is selected at the multiplexer, and wherein writing the test write data to the memory array comprises:

outputting, by a test register, the test write data;

receiving, by the multiplexer at the second input node, the test write data;

latching, at a latch circuit, the test write data; and

providing, by the latch circuit, the test write data to the memory cell array.

16. The method of claim 15 , further comprising:

setting, by a test control circuit, the test write data into the test register.

17. An apparatus comprising:

a memory array;

a read data path;

an output buffer having an output node coupled to an external terminal;

an input receiver having an input node coupled to the external terminal;

a test register;

a comparator coupled to the test register and the read data path;

a test read data path configured to bypass the output buffer and the input receiver:

a test control circuit coupled to the test register and the comparator, and

a test terminal coupled to the test control circuit.

18. The apparatus of claim 17 , wherein the comparator is configured to generate a comparison result signal based at least in part on receiving test read data from the memory array via the read data path and receiving a value from the test register.

19. The apparatus of claim 17 , wherein the test control circuit is configured to receive a first signal from the comparator for a test read operation and provide a second signal to the test register for a test write operation.

20. An apparatus comprising:

a memory array;

a read data path;

an output buffer having an output node coupled to an external terminal;

an input receiver having an input node coupled to the external terminal:

a test register;

a comparator coupled to the test register and the read data path, wherein the comparator is configured to generate a comparison result signal based at least in part on receiving test read data from the memory array via the read data path and receiving a value from the test register;

a test read data path configured to bypass the output buffer and the input receiver;

a test control circuit coupled to the test register and the comparator, wherein the test control circuit is configured to receive the comparison result signal from the comparator and generate a pass/fail signal based on the comparison result signal; and

a test terminal coupled to the test control circuit.