Semiconductor deposition reactor manifolds
The present disclosure pertains to embodiments of a semiconductor deposition reactor manifold and methods of using the semiconductor deposition reactor manifold which can be used to deposit semiconductor layers using processes such as atomic layer deposition (ALD). The semiconductor deposition reactor manifold has a bore, a first supply channel, and a second supply channel. Advantageously, the first supply channel and the second supply channel merge with the bore in an offset fashion which leads to reduced cross-contamination within the supply channels.
1. A semiconductor processing device comprising:
a manifold comprising:
a bore configured to deliver vaporized reactant to a reactor, the bore comprising straight walls parallel to a longitudinal axis;
an upper wall disposed at an upper portion of the manifold, the upper wall defining a capping surface at a first end of the bore along the longitudinal axis;
an outlet at a lower portion of the manifold along the longitudinal axis, the outlet configured to deliver gas to the reactor;
a first supply channel configured to supply gas to the bore; and
a second supply channel configured to supply gas to the bore,
wherein the first supply channel merges with the bore at an angle greater than 90 degrees with respect to a length of the bore above the first supply channel and the second supply channel merges with the bore at an angle less than 90 degrees with respect to a length of the bore above the second supply channel,
wherein an inlet opening of the first supply channel merges with the bore at a first position along the longitudinal axis, and wherein an inlet opening of the second supply channel merges with the bore at a second position along the longitudinal axis, the first position different from the second position.
2. The semiconductor processing device of claim 1 , wherein the capping surface is shaped to redirect upwardly directed gas downwardly back through the bore to the outlet.
3. The semiconductor processing device of claim 1 , further comprising a first block mounted to the manifold, the first block and the manifold cooperating to at least partially define the first supply channel.
4. The semiconductor processing device of claim 3 , further comprising a second block mounted to the manifold, the second block and the manifold cooperating to at least partially define the second supply channel.
5. The semiconductor processing device of claim 1 , wherein the first supply channel is in fluid communication with a first reactant source and is configured to deliver a first vaporized reactant to the bore, and wherein the second supply channel is in fluid communication with a second reactant source and is configured to deliver a second vaporized reactant to the bore.
6. The semiconductor processing device of claim 1 , wherein the first supply channel is in fluid communication with an inactive gas to purge the bore.
7. The semiconductor processing device of claim 1 , further comprising a showerhead device below the outlet, the showerhead device configured to disperse a flow of the gas from the outlet.
8. The semiconductor processing device of claim 7 , further comprising a reaction chamber below the showerhead device and a substrate support configured to support a substrate in the reaction chamber.
9. The semiconductor processing device of claim 3 , wherein the first block comprises a first vapor phase inlet configured to input a first reactant into the first supply channel.
10. The semiconductor processing device of claim 9 , wherein the first block further comprises a second vapor phase inlet and a third vapor phase inlet.
11. The semiconductor processing device of claim 10 , wherein the first block further comprises a fourth vapor phase inlet, wherein the fourth vapor phase inlet is located on a lateral side of the first block opposite to the manifold.
12. The semiconductor processing device of claim 11 , wherein the fourth vapor phase inlet is configured to input a purge gas into the manifold.
13. The semiconductor processing device of claim 1 , wherein the first supply channel is angled towards the capping surface and the second supply channel is angled towards the outlet, the second supply channel downstream of the first supply channel.
14. The semiconductor processing device of claim 1 , wherein the manifold comprises a single monolithic block.
15. The semiconductor processing device of claim 1 , wherein the bore extends continuously along the longitudinal axis.
16. A semiconductor processing device comprising:
a manifold comprising a bore configured to deliver gas to a reaction chamber, the bore comprising straight walls parallel to a longitudinal axis;
an upper wall disposed at an upper portion of the manifold, the upper wall defining a capping surface at a first end of the bore along the longitudinal axis;
a first supply line configured to supply an inactive purge gas to the bore at a first location along the longitudinal axis downstream of the capping surface, wherein the first supply line is coupled with the bore at an obtuse angle with respect to an upper length of the bore so as to direct the inactive purge gas toward the capping surface;
a second supply line configured to supply a gas to the bore at a second location along the longitudinal axis, the second location different from the first location, wherein the second supply line is coupled with the bore at an acute angle with respect to the upper length of the bore so as to direct the gas toward the outlet at a lower portion of the manifold along the longitudinal axis and
wherein an inlet opening of each of the first and second supply lines merges into the bore.
17. The semiconductor processing device of claim 16 , wherein the first supply line is connected to an inactive gas source to purge the bore.
18. The semiconductor processing device of claim 16 , wherein the inactive gas comprises at least one of argon gas and nitrogen gas.