Moisture barrier for bond pads and integrated circuit having the same
A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.
1. A semiconductor die comprising:
a substrate layer;
one or more metal layers disposed over the substrate layer;
one or more polymer interlevel dielectric layers disposed over the substrate, at least one of the one or more polymer interlevel dielectric layers spaced from the one or more metal layers by a trench so that the one or more polymer interlevel dielectric layers are spaced apart from the one or more metal layers; and
a topcoat insulation layer disposed over the one or more metal layers and the one or more polymer interlevel dielectric layers and defining a top surface of the die,
wherein the top coat insulation layer is impervious to moisture and wherein the trench inhibits migration of moisture to the one or more metal layers, thereby preventing metal migration from the one or more metal layers.
2. The semiconductor die of claim 1 wherein the trench is filled by one of: at least a portion of the topcoat insulation layer, at least a portion of one or more metal layers, and at least a portion of another of the one or more polymer interlevel dielectric layers.
3. The semiconductor die of claim 1 wherein the one or more polymer interlevel dielectric layers are a first polyimide layer and a second polyimide layer.
4. The semiconductor die of claim 1 wherein the one or more metal layers are one or more electrodes of a bond pad.
5. The semiconductor die of claim 1 further comprising one or more insulation layers disposed at least partially over the substrate layer.
6. The semiconductor die of claim 1 wherein the trench is defined in the one or more polymer interlevel dielectric layers.
7. The semiconductor die of claim 1 wherein the trench tapers toward the substrate layer.
8. The semiconductor die of claim 6 wherein the trench in each of the one or more polymer interlevel dielectric layers is stepped relative to each other.
9. The semiconductor die of claim 1 wherein the trench circumscribes a bond pad of the semiconductor die defined at least in part by the one or more metal layers.
10. A radiofrequency module, comprising:
a printed circuit board;
a semiconductor die mounted on the printed circuit board and including (a) a substrate layer, (b) one or more metal layers disposed over the substrate layer, (c) one or more polymer interlevel dielectric layers disposed over the substrate, at least one of the one or more polymer interlevel dielectric layers spaced from the one or more metal layers by a trench so that the one or more polymer interlevel dielectric layers are spaced apart from the one or more metal layers, and (d) a topcoat insulation layer disposed over the one or more metal layers and the one or more polymer interlevel dielectric layers and defining a top surface of the die, the topcoat insulation layer being impervious to moisture and the trench inhibiting migration of moisture to the one or more metal layers, thereby preventing metal migration from the one or more metal layers.
11. The radiofrequency module of claim 10 wherein the trench is filled by one of: at least a portion of the topcoat insulation layer, at least a portion of one or more metal layers, and at least a portion of another of the one or more polymer interlevel dielectric layers.
12. The radiofrequency module of claim 10 wherein the one or more polymer interlevel dielectric layers are a first and second polyimide layers.
13. The radiofrequency module of claim 10 wherein the one or more metal layers are one or more electrodes of a bond pad.
14. The radiofrequency module of claim 10 further comprising one or more insulation layers disposed at least partially over the substrate layer.
15. The radiofrequency module of claim 10 wherein the trench is defined in the one or more polymer interlevel dielectric layers.
16. The radiofrequency module of claim 10 wherein the trench tapers toward the substrate layer.
17. A wireless mobile device comprising:
one or more antennas;
a front end system that communicates with the one or more antennas; and
a semiconductor die including (a) a substrate layer, (b) one or more metal layers disposed over the substrate layer, (c) one or more polymer interlevel dielectric layers disposed over the substrate, at least one of the one or more polymer interlevel dielectric layers spaced from the one or more metal layers by a trench so that the one or more polymer interlevel dielectric layers are spaced apart from the one or more metal layers, and (d) a topcoat insulation layer disposed over the one or more metal layers and the one or more polymer interlevel dielectric layers and defining a top surface of the die, the topcoat insulation layer being impervious to moisture and the trench inhibiting migration of moisture to the one or more metal layers, thereby preventing metal migration from the one or more metal layers.
18. The wireless mobile device of claim 17 wherein the trench is filled by one of: at least a portion of the topcoat insulation layer, at least a portion of one or more metal layers, and at least a portion of another of the first and second polymer interlevel dielectric layers.
19. The wireless mobile device of claim 17 wherein the one or more polymer interlevel dielectric layers are a first and second polyimide layers.
20. The wireless mobile device of claim 17 wherein the trench is defined in the one or more polymer interlevel dielectric layers.