Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages
Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.
1. A configuration of nanosheet field effect transistor (FET) devices in a first region of a substrate;
wherein each of the nanosheet FET devices in the first region includes:
a first channel nanosheet;
a second channel nanosheet over the first channel nanosheet;
a first gate structure around the first channel nanosheet;
a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure; and
a dopant-passageway air gap between the first gate structure and the second gate structure, wherein the dopant-passageway air gap allows dopants to enter the dopant-passageway air gap and enter the first gate structure and the second gate structure from the dopant-passageway air gap to form a doped region of the first gate structure and a doped region of the second gate structure.
2. The substrate of claim 1 further comprising nanosheet FET devices in a second region of the substrate.
3. The substrate of claim 2 , wherein each of the nanosheet FET devices in the second region includes a third channel nanosheet.
4. The substrate of claim 3 , wherein each of the nanosheet FET device in the second region includes a fourth channel nanosheet over the third channel nanosheet.
5. The substrate of claim 4 , wherein each of the nanosheet FET device in the second region includes a third gate structure around the third channel nanosheet.
6. The substrate of claim 5 , wherein each of the nanosheet FET device in the second region includes a fourth gate structure around the fourth channel nanosheet.
7. The substrate of claim 6 , wherein a gap is between the third gate structure and the fourth gate structure.
8. The substrate of claim 7 , wherein the third gate structure and the fourth gate structure pinch off in the gap between the third gate structure and the fourth gate structure.
9. The substrate of claim 8 , wherein at least a portion of the pinch off area is undoped.
10. The substrate of claim 1 further comprising a cap layer formed over the first region and within a portion of the dopant-passageway air gap between the first gate structure and the second gate structure.