Display device

1. A display device, comprising:

a first voltage line disposed on a substrate, a first power supply voltage being applied to the first voltage line;

a buffer layer disposed on the first voltage line;

a first transistor including a semiconductor pattern disposed on the buffer layer;

a first insulating layer disposed on the semiconductor pattern of the first transistor;

a first capacitor electrode disposed on the first insulating layer;

a second insulating layer disposed on the first capacitor electrode;

a first electrode and a second electrode disposed on the second insulating layer and spaced apart from each other, and

a second voltage line disposed on the substrate, a second power supply voltage being applied to the second voltage line, wherein

the second electrode is electrically connected to the first voltage line,

the first voltage line overlaps the first capacitor electrode in a thickness direction of the substrate,

the buffer layer is disposed on the second voltage line, and

the second voltage line overlaps the second electrode in the thickness direction of the substrate.

2. The display device of claim 1 , further comprising:

a second capacitor electrode disposed on the second insulating layer and overlapping the first capacitor electrode in the thickness direction of the substrate, wherein

the first electrode and the second electrode are disposed on the second capacitor electrode, and

the second capacitor electrode overlaps the first voltage line in the thickness direction of the substrate.

3. The display device of claim 2 , further comprising:

a third capacitor electrode disposed on the first insulating layer and overlapping the first capacitor electrode in the thickness of the substrate; and

a third insulating layer disposed on the third capacitor electrode, wherein

the first capacitor electrode is disposed on the third insulating layer, and

the third capacitor electrode overlaps the first voltage line in the thickness direction of the substrate.

4. The display device of claim 3 , wherein

the third capacitor electrode overlaps the second capacitor electrode in the thickness direction of the substrate, and

the second capacitor electrode is electrically connected to the third capacitor electrode through a contact hole penetrating the second insulating layer and the third insulating layer.

5. The display device of claim 2 , wherein the first electrode is electrically connected to the second capacitor electrode.

6. The display device of claim 5 , wherein

the second capacitor electrode overlaps the first electrode in the thickness direction of the substrate, and

the second capacitor electrode is disposed between the first electrode and the first voltage line.

7. The display device of claim 2 , further comprising:

a light blocking layer disposed on the substrate, wherein

the buffer layer is disposed on the light blocking layer, and

the second capacitor electrode is electrically connected to the light blocking layer.

8. The display device of claim 1 , wherein the first transistor comprises:

a gate electrode disposed on the first insulating layer; and

a first electrode disposed on the second insulating layer,

wherein the first electrode of the first transistor is electrically connected to the second voltage line.

9. The display device of claim 1 , further comprising:

a second transistor including:

a semiconductor pattern disposed on the buffer layer; and

a first electrode disposed on the first insulating layer; and

a second capacitor electrode disposed on the second insulating layer, wherein

the first electrode of the second transistor is electrically connected to the semiconductor pattern of the second transistor through a first contact hole penetrating the first insulating layer, and

the second capacitor electrode does not overlap the first contact hole in the thickness direction of the substrate.

10. The display device of claim 1 , further comprising:

a second transistor including a semiconductor pattern disposed on the buffer layer;

a gate electrode of the first transistor disposed on the first insulating layer;

a third insulating layer disposed on the gate electrode of the first transistor, wherein

the second transistor includes a first electrode disposed on the third insulating layer,

the first transistor includes a first electrode disposed on the second insulating layer,

the second insulating layer is disposed on the third insulating layer,

the first electrode of the second transistor is electrically connected to the gate electrode of the first transistor through a first contact hole penetrating the third insulating layer, and

the first electrode of the first transistor does not overlap the first contact hole in the thickness direction of the substrate.

11. The display device of claim 10 , further comprising:

a second capacitor electrode disposed on the second insulating layer and overlapping the first capacitor electrode in the thickness direction of the substrate,

wherein the second capacitor electrode does not overlap the first contact hole in the thickness direction of the substrate.

12. The display device of claim 1 , further comprising:

a light emitting element disposed on the first electrode and the second electrode, wherein

an end of the light emitting element is electrically connected to the first electrode, and

another end of the light emitting element is electrically connected to the second electrode.

13. A display device, comprising:

a first voltage line disposed on a substrate, a first power supply voltage being applied to the first voltage line;

a buffer layer disposed on the first voltage line;

a semiconductor layer disposed on the buffer layer and including a semiconductor pattern of a first transistor and a semiconductor pattern of a second transistor;

a first insulating layer disposed on the semiconductor layer;

a first conductive layer disposed on the first insulating layer and including a gate electrode of the first transistor;

a second insulating layer disposed on the first conductive layer;

a second conductive layer disposed on the second insulating layer and including a first capacitor electrode and a first electrode of the second transistor;

a third insulting layer disposed on the second conductive layer;

a third conductive layer disposed on the third insulating layer and including a first electrode of the first transistor, wherein

the first electrode of the second transistor is electrically connected to the gate electrode of the first transistor through a first contact hole penetrating the second insulating layer,

the third conductive layer does not overlap the first contact hole in a thickness direction of the substrate,

the third conductive layer includes a second capacitor electrode, and

the second capacitor electrode overlaps the first capacitor electrode in the thickness direction of the substrate.

14. The display device of claim 13 , wherein

the first electrode of the second transistor is electrically connected to the semiconductor pattern of the second transistor through a second contact hole penetrating the first insulating layer and the second insulating layer, and

the third conductive layer does not overlap the second contact hole in the thickness direction of the substrate.

15. The display device of claim 13 , further comprising:

a fourth insulating layer disposed on the third conductive layer; and

a first electrode and a second electrode disposed on the fourth insulating layer and spaced apart from each other, wherein

the second electrode is electrically connected to the first voltage line, and

the first voltage line overlaps the first capacitor electrode in the thickness direction of the substrate.

16. The display device of claim 15 , wherein

the first conductive layer includes a third capacitor electrode overlapping the first capacitor electrode in the thickness direction of the substrate, and

the third capacitor electrode is electrically connected to the second capacitor electrode.

17. The display device of claim 13 , further comprising:

a second voltage line disposed on the substrate, a second power supply voltage being applied to the second voltage line,

wherein the buffer layer is disposed on the second voltage line.