Reduced-complexity maximum likelihood sequence detector suitable for m-ary signaling

1. A receiver comprising:

a decision feedback equalizer that derives an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and

a reduced-complexity maximum likelihood sequence detector (rMLSD) that derives a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.

2. The receiver of claim 1 , wherein the decision feedback equalizer comprises:

a summer that combines a feedback signal with the filtered receive signal to produce an equalized signal;

a slicer that derives the initial sequence of symbol decisions from the equalized signal; and

a feedback filter that derives the feedback signal from the initial sequence of symbol decisions.

3. The receiver of claim 2 , wherein the slicer further derives the second most likely symbol decision for each symbol decision in the initial sequence.

4. The receiver of claim 1 , wherein the decision feedback equalizer comprises:

a precompensation unit that derives tentative symbol decisions from the filtered receive signal; and

a multiplexer that selects from the tentative symbol decisions based on preceding symbol decisions in the initial sequence.

5. The receiver of claim 4 , further comprising:

an error calculation circuit that determines an equalization error based on the initial sequence of symbol decisions; and

a competing symbol decision circuit that determines the second most likely symbol decisions based on the equalization error and the initial sequence of symbol decisions.

6. The receiver of claim 1 , wherein the rMLSD comprises:

branch metric calculation circuitry that combines the filtered receive signal with symbol decisions from the initial sequence and with associated second most likely symbol decisions to determine corresponding branch metrics, and that sums each branch metric with each preceding state metric to obtain path metrics;

comparators that determine a minimum path metric for each symbol decision in the initial sequence and each second most likely symbol decision; and

a pair of copy-shift registers that respond to outputs of the comparators to assemble a most likely symbol decision sequence ending in that symbol decision and that second most likely symbol decision.

7. The receiver of claim 6 , wherein the rMLSD further comprises a state metric comparator that selects the most likely symbol decision sequence, taking a symbol decision from a front of that sequence as a symbol decision for the final sequence.

8. A receiving method comprising:

deriving an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and

using a reduced-complexity maximum likelihood sequence detector (rMLSD) to derive a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.

9. The receiving method of claim 8 , wherein as part of deriving the final sequence of symbol decisions, the rMLSD:

combines the filtered receive signal or initial equalization error signals with symbol decisions from the initial sequence and with associated second most likely symbol decisions to determine corresponding equalization errors;

sums each equalization error with each preceding state metric to obtain branch metrics;

determines a minimum path metric for each symbol decision in the initial sequence and each second most likely symbol decision;

assembles a first sequence that ends with that symbol decision from the initial sequence; and

assembles a second sequence that ends with an associated second most likely symbol decision.

10. The receiving method of claim 9 , wherein as part of deriving the final sequence of symbol decisions, the rMLSD further:

compares state metrics for the first and second sequences; and

provides a symbol decision from a front of a selected one of the first and second sequences as a symbol decision for the final sequence.

11. The receiving method of claim 8 , wherein said deriving the initial sequence of symbol decisions is performed by:

combining a feedback signal with the filtered receive signal to produce an equalized signal;

comparing the equalized signal to a set of thresholds to obtain the initial sequence of symbol decisions; and

converting the initial sequence of symbol decisions into the feedback signal.

12. The receiving method of claim 11 , further comprising comparing the equalized signal to a set of target symbol levels to derive the second most likely symbol decision for each symbol decision in the initial sequence.

13. The receiving method of claim 8 , wherein said deriving the initial sequence of symbol decisions comprises:

converting the filtered receive signal into tentative symbol decisions using a precompensation unit; and

using previous symbol decisions in the initial sequence to select from the tentative symbol decisions.

14. The receiving method of claim 13 , further comprising:

combining the filtered receive signal with the initial sequence of symbol decisions to determine an initial equalization error; and

determining the second most likely symbol decisions based on the initial equalization error and the initial sequence of symbol decisions.

15. A semiconductor intellectual property core that generates circuitry comprising:

an initial equalizer that derives an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and

a reduced-complexity maximum likelihood sequence detector (rMLSD) that derives a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.

16. The semiconductor intellectual property core of claim 15 , wherein the rMLSD comprises:

branch metric calculation circuitry that combines the filtered receive signal or an initial equalization error signal with symbol decisions from the initial sequence and with associated second most likely symbol decisions to determine corresponding equalization errors, and that sums each equalization error with each preceding state metric to obtain branch metrics;

comparators that determine a minimum path metric for each symbol decision in the initial sequence and each second most likely symbol decision; and

a pair of copy-shift registers that respond to outputs of the comparators to assemble first and second symbol decision sequences for said minimum path metrics.

17. The semiconductor intellectual property core of claim 16 , wherein the MLSD further comprises a state metric comparator that selects one of said first and second symbol decision sequences and provides a symbol decision from a front of the selected symbol decision sequence as a symbol decision for the final sequence.

18. The semiconductor intellectual property core of claim 15 , wherein the initial equalizer comprises:

a summer that combines a feedback signal with the filtered receive signal to produce an equalized signal;

a slicer that derives the initial sequence of symbol decisions from the equalized signal; and

a feedback filter that derives the feedback signal from the initial sequence of symbol decisions.

19. The semiconductor intellectual property core of claim 18 , wherein the slicer further derives the second most likely symbol decision for each symbol decision in the initial sequence.

20. The semiconductor intellectual property core of claim 15 , wherein the initial equalizer comprises:

a precompensation unit that derives tentative symbol decisions from the filtered receive signal; and

a multiplexer that selects from the tentative symbol decisions based on preceding symbol decisions in the initial sequence.