Memory device detecting defect by measuring line resistance of word line

1. A memory device comprising:

a memory cell array including memory cells respectively arranged in regions wherein word lines and bit lines intersect;

a row decoder configured to select a word line as a selected word line from among the word lines in response to a received address; and

control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line,

wherein the control logic is configured to measure a line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.

2. The memory device of claim 1 , wherein the line resistance of the selected word line is a resistance in a path between the selected word line and the row decoder.

3. The memory device of claim 1 , wherein the control logic further includes a first switch initializing the sensing capacitor, and a second switch connecting the selected word line to the sensing capacitor.

4. The memory device of claim 3 , wherein the control logic further includes a comparator configured to receive a sense voltage from the sensing capacitor, receive a reference voltage, compare the sense voltage and the reference voltage, and provide a comparison result based on the comparing of the sense voltage and the reference voltage, and

the control logic measures the voltage of the sensing capacitor following the performing of the charge sharing operation with reference to the comparison result.

5. The memory device of claim 3 , wherein the control logic further includes a voltage driver providing a charge voltage, and a third switch connecting the selected word line to the voltage driver.

6. The memory device of claim 5 , wherein

upon connecting the selected word line to the voltage driver, the charge voltage is provided to the selected word line to provide an electrical charge to the word line capacitor, and

upon connecting the selected word line to the sensing capacitor, the electrical charge provided to the word line capacitor is shared with the sensing capacitor.

7. The memory device of claim 6 , wherein the word line capacitor is a capacitor existing between the selected word line and word lines adjacent to the selected word line among the word lines.

8. The memory device of claim 3 , wherein the row decoder includes a voltage driver providing a charge voltage, and a third switch connecting the selected word line to the voltage driver.

9. The memory device of claim 8 , wherein

upon connecting the selected word line to the voltage driver, the charge voltage is provided to the selected word line to provide an electrical charge to the word line capacitor, and

upon connecting the selected word line to the sensing capacitor, the electrical charge provided to the word line capacitor is shared with the sensing capacitor.

10. The memory device of claim 9 , wherein the word line capacitor is a capacitor existing between the selected word line and word lines adjacent to the selected word line among the word lines.

11. A memory device comprising:

a memory cell array including memory cells respectively arranged in regions wherein word lines and bit lines intersect;

a row decoder configured to select one word line as a selected word line from among the word lines in response to a received address; and

control logic configured to measure a line resistance of the selected word line, wherein the control logic includes:

a sensing capacitor;

a voltage driver providing a charge voltage;

a first switch having a first end connected to the voltage driver and a second end;

a second switch having a first end connected to the selected word line and a second end connected to the second end of the first switch;

a third switch having a first end connected between the first switch and the second switch and a second end;

a fourth switch connected in parallel with the sensing capacitor and connected to the second end of the third switch; and

a comparator including a first input terminal receiving a sense voltage from the sensing capacitor and a second input terminal receiving a reference voltage.

12. The memory device of claim 11 , wherein the control logic turns ON the first switch and the second switch during a precharge period to provide the charge voltage to the selected word line from the voltage driver.

13. The memory device of claim 12 , wherein the control logic turns ON the fourth switch during the precharge period to initialize the sensing capacitor.

14. The memory device of claim 12 , wherein the control logic turns OFF the first switch and the fourth switch, and turns ON the third switch during a sensing period following the precharge period to perform a charge sharing operation between the selected word line and the sensing capacitor.

15. The memory device of claim 14 , wherein following the charge sharing operation, the comparator compares the sense voltage with the reference voltage to generate a comparison result, and

the control logic measures the line resistance of the selected word line with reference to the comparison result.

16. A memory device comprising:

a memory cell array including memory cells respectively arranged in regions wherein word lines and bit lines intersect;

a row decoder configured to select a word line as a selected word line from among the word lines in response to a received address; and

control logic including a data access unit configured to perform at least one data access operation in relation to a memory cell connected to the selected word line, and a test unit including a sensing capacitor,

wherein the test unit is configured to measure a line resistance of the selected word line and measure a leakage current associated with the selected word line by

performing a charge sharing operation between the selected word line and the sensing capacitor,

measuring a voltage of the sensing capacitor during a first time period following the performing of the charge sharing operation to measure the line resistance of the selected word line, and

measuring the voltage of the sensing capacitor during a second time period following the first time period to measure the leakage current associated with the selected word line.

17. The memory device of claim 16 , wherein a size of the sensing capacitor is proportional to a size of a word line capacitor associated with the selected word line.

18. The memory device of claim 16 , wherein the test unit includes a switch connected in parallel with the sensing capacitor and commonly connected to a sensing node with the sensing capacitor.

19. The memory device of claim 18 , wherein the test unit further includes a comparator including a first input terminal connected to the sensing node and receiving a sense voltage from the sensing capacitor, and a second input terminal receiving a reference voltage,

the comparator configured to compare the sense voltage with the reference voltage during the first time period to measure the line resistance of the selected word line, and further configured to compare the sense voltage with the reference voltage during the second time period to measure the leakage current of the selected word line.

20. The memory device of claim 19 , wherein the control logic includes a voltage driver applying a charge voltage to the selected word line to precharge the selected word line with an electrical charge, and thereafter,

the charge sharing operation shares the electrical charge between the selected word line and the sensing capacitor.