Cache line coherence state upgrade
Techniques for performing cache operations are provided. The techniques include, recording an entry indicating that a cache line is exclusive-upgradeable; removing the cache line from a cache; and converting a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.
1. A method, comprising:
recording an entry indicating that a cache line is exclusive-upgradeable;
removing the cache line from a cache; and
converting a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.
2. The method of claim 1 , wherein recording the entry is performed in response to upgrading the cache line to an exclusive state.
3. The method of claim 2 , wherein prior to upgrading the cache line to the exclusive state, the cache line is in the cache in a non-exclusive state.
4. The method of claim 3 , wherein the cache line is brought into the cache in a non-exclusive state in response to a cache miss.
5. The method of claim 3 , wherein the cache line is in the cache in the non-exclusive state as a result of a memory access instruction that is a type that results in cache lines being brought into the cache in a non-exclusive state, unless the cache line is exclusive-upgradeable.
6. The method of claim 5 , wherein the memory access instruction is a load instruction.
7. The method of claim 2 , wherein removing the cache line from the cache is performed in response to determining that a global invalidation request is transmitted for the cache line.
8. The method of claim 2 , wherein recording the entry in response to upgrading the cache line in the cache to the exclusive state comprises determining that a store instruction is performed for the cache line while the cache line is in a non-exclusive state.
9. The method of claim 2 , wherein upgrading the cache line in the cache to the exclusive state is performed in response to a request to access the cache line in an exclusive state.
10. The method of claim 9 , wherein the request to access the cache line in the exclusive state is associated with a store instruction.
11. The method of claim 1 , wherein removing the cache line from the cache occurs due to an eviction or an invalidating probe.
12. The method of claim 1 , wherein converting the request to the request to insert the cache line in the cache in the exclusive state comprises detecting the entry indicating that the cache line is exclusive-upgradeable.
13. The method of claim 1 , wherein the request to insert the cache line into the cache includes a coherence state-agnostic request.
14. The method of claim 1 , wherein the request to insert the cache line in the cache includes a request to insert the cache line in a non-exclusive state.
15. The method of claim 1 , wherein the entry is stored in a metadata memory.
16. The method of claim 1 , wherein converting the request to insert the cache line into the cache into the request to insert the cache line in the cache in the exclusive state is performed regardless of a type of the request.
17. A system, comprising:
a cache; and
a cache controller configured to:
record an entry indicating that a cache line is exclusive-upgradeable;
remove the cache line from the cache; and
convert a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.
18. The system of claim 17 , wherein recording the entry is performed in response to upgrading the cache line to an exclusive state.
19. The system of claim 18 , wherein prior to upgrading the cache line to the exclusive state, the cache line is in the cache in a non-exclusive state.
20. The system of claim 19 , wherein the cache line is brought into the cache in a non-exclusive state in response to a cache miss.
21. The system of claim 19 , wherein the cache line is in the cache in the non-exclusive state as a result of a memory access instruction that is a type that results in cache lines being brought into the cache in a non-exclusive state, unless the cache line is exclusive-upgradeable.
22. The system of claim 21 , wherein the memory access instruction is a load instruction.
23. The system of claim 18 , wherein removing the cache line from the cache is performed in response to determining that a global invalidation request is transmitted for the cache line.
24. The system of claim 18 , wherein recording the entry in response to upgrading the cache line in the cache to the exclusive state comprises determining that a store instruction is performed for the cache line while the cache line is in a non-exclusive state.
25. The system of claim 18 , wherein upgrading the cache line in the cache to the exclusive state is performed in response to a request to access the cache line in an exclusive state.
26. The system of claim 25 , wherein the request to access the cache line in the exclusive state is associated with a store instruction.
27. The system of claim 17 , wherein removing the cache line from the cache occurs due to or an invalidating probe.
28. The system of claim 17 , wherein converting the request to the request to insert the cache line in the cache in the exclusive state comprises detecting the entry indicating that the cache line is exclusive-upgradeable.
29. The system of claim 17 , wherein the request to insert the cache line in the cache includes a coherence state-agnostic request.
30. The system of claim 17 , wherein the request to insert the cache line in the cache includes a request to insert the cache line in a non-exclusive state.
31. The system of claim 17 , wherein the entry is stored in a metadata memory.
32. The system of claim 17 , wherein converting the request to insert the cache line into the cache into the request to insert the cache line in the cache in the exclusive state is performed regardless of a type of the request.
33. A system, comprising:
a processor;
a cache; and
a cache controller configured to:
record an entry indicating that a cache line is exclusive-upgradeable;
remove the cache line from the cache; and
convert a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.
34. The system of claim 33 , wherein recording the entry is performed in response to upgrading the cache line to an exclusive state.
35. The system of claim 34 , wherein prior to upgrading the cache line to the exclusive state, the cache line is in the cache in a non-exclusive state.
36. The system of claim 35 , wherein the cache line is brought into the cache in a non-exclusive state in response to a cache miss.
37. The system of claim 35 , wherein the cache line is in the cache in the non-exclusive state as a result of a memory access instruction that is a type that results in cache lines being brought into the cache in a non-exclusive state, unless the cache line is exclusive-upgradeable.
38. The system of claim 37 , wherein the memory access instruction is a load instruction.
39. The system of claim 34 , wherein removing the cache line from the cache is performed in response to determining that a global invalidation request is transmitted for the cache line.
40. The system of claim 34 , wherein recording the entry in response to upgrading the cache line in the cache to the exclusive state comprises determining that a store instruction is performed for the cache line while the cache line is in a non-exclusive state.
41. The system of claim 34 , wherein upgrading the cache line in the cache to the exclusive state is performed in response to a request to access the cache line in an exclusive state.
42. The system of claim 41 , wherein the request to access the cache line in the exclusive state is associated with a store instruction.
43. The system of claim 33 , wherein removing the cache line from the cache occurs due to an eviction or an invalidating probe.
44. The system of claim 33 , wherein converting the request to the request to insert the cache line in the cache in the exclusive state comprises detecting the entry indicating that the cache line is exclusive-upgradeable.
45. The system of claim 33 , wherein the request to insert the cache line into the cache includes a coherence state-agnostic request.
46. The system of claim 33 , wherein the request to insert the cache line in the cache includes a request to insert the cache line in a non-exclusive state.
47. The system of claim 33 , wherein the entry is stored in a metadata memory.
48. The system of claim 33 , wherein converting the request to insert the cache line into the cache into the request to insert the cache line in the cache in the exclusive state is performed regardless of a type of the request.